drivers/crypto/caam/ctrl.c

1099

wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);

drivers/crypto/caam/ctrl.c

143

wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));

drivers/crypto/caam/ctrl.c

387

wr_reg32(&r4tst->rtfrqmin, val >> 2);

drivers/crypto/caam/ctrl.c

389

wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);

drivers/crypto/caam/ctrl.c

392

wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |

drivers/crypto/caam/ctrl.c

400

wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);

drivers/crypto/caam/ctrl.c

401

wr_reg32(&r4tst->rtpkrrng, 570);

drivers/crypto/caam/ctrl.c

402

wr_reg32(&r4tst->rtpkrmax, 1600);

drivers/crypto/caam/ctrl.c

403

wr_reg32(&r4tst->rtscml, (122 << 16) | 317);

drivers/crypto/caam/ctrl.c

404

wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);

drivers/crypto/caam/ctrl.c

405

wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);

drivers/crypto/caam/ctrl.c

406

wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);

drivers/crypto/caam/ctrl.c

407

wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);

drivers/crypto/caam/ctrl.c

408

wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);

drivers/crypto/caam/ctrl.c

409

wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);

drivers/crypto/caam/ctrl.c

803

wr_reg32(&ctrl->mcr, state->mcr);

drivers/crypto/caam/ctrl.c

804

wr_reg32(&ctrl->scfgr, state->scfgr);

drivers/crypto/caam/ctrl.c

809

wr_reg32(&ctrl->deco_mid[i].liodn_ms,

drivers/crypto/caam/ctrl.c

811

wr_reg32(&ctrl->deco_mid[i].liodn_ls,

drivers/crypto/caam/ctrl.c

818

wr_reg32(&ctrl->jr_mid[i].liodn_ms,

drivers/crypto/caam/ctrl.c

820

wr_reg32(&ctrl->jr_mid[i].liodn_ls,

drivers/crypto/caam/jr.c

153

wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);

drivers/crypto/caam/jr.c

249

wr_reg32(&jrp->rregs->jrintstatus, irqstate);

drivers/crypto/caam/jr.c

313

wr_reg32(&jrp->rregs->outring_rmvd, 1);

drivers/crypto/caam/jr.c

485

wr_reg32(&jrp->rregs->inpring_jobadd, 1);

drivers/crypto/caam/jr.c

504

wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH);

drivers/crypto/caam/jr.c

505

wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH);

drivers/crypto/caam/jr.c

94

wr_reg32(&jrp->rregs->jrcommand, jrcr_bits);

drivers/crypto/caam/regs.h

101

static inline void wr_reg32(void __iomem *reg, u32 data)

drivers/tty/synclink_gt.c

2132

wr_reg32(info, RDCSR, status); /* clear pending */

drivers/tty/synclink_gt.c

2157

wr_reg32(info, TDCSR, status); /* clear pending */

drivers/tty/synclink_gt.c

2303

wr_reg32(info, IOSR, changed);

drivers/tty/synclink_gt.c

2813

wr_reg32(info, XSR, xsync);

drivers/tty/synclink_gt.c

2850

wr_reg32(info, XCR, xctrl);

drivers/tty/synclink_gt.c

2883

wr_reg32(info, IODR, data);

drivers/tty/synclink_gt.c

2889

wr_reg32(info, IOVR, data);

drivers/tty/synclink_gt.c

2994

wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);

drivers/tty/synclink_gt.c

3016

wr_reg32(info, IOER, 0);

drivers/tty/synclink_gt.c

3775

wr_reg32(info, RDCSR, BIT1);

drivers/tty/synclink_gt.c

3788

wr_reg32(info, TDCSR, BIT1);

drivers/tty/synclink_gt.c

3890

wr_reg32(info, RDCSR, BIT6);

drivers/tty/synclink_gt.c

3896

wr_reg32(info, RDDAR, info->rbufs[0].pdesc);

drivers/tty/synclink_gt.c

3900

wr_reg32(info, RDCSR, (BIT2 + BIT0));

drivers/tty/synclink_gt.c

3903

wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));

drivers/tty/synclink_gt.c

3948

wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);

drivers/tty/synclink_gt.c

3949

wr_reg32(info, TDCSR, BIT2 + BIT0);

drivers/tty/synclink_gt.c

406

static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);