drivers/gpu/drm/i915/display/i9xx_wm.c

130

vlv_punit_write(display, PUNIT_REG_DDR_SETUP2, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

153

vlv_punit_write(display, PUNIT_REG_DSPSSPM, val);

drivers/gpu/drm/i915/display/i9xx_wm.c

3935

vlv_punit_write(display, PUNIT_REG_DDR_SETUP2, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

702

vlv_punit_write(display, PUNIT_REG_DSPSSPM, val);

drivers/gpu/drm/i915/display/intel_cdclk.c

787

vlv_punit_write(display, PUNIT_REG_DSPSSPM, val);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1200

vlv_punit_write(display, PUNIT_REG_PWRGT_CTRL, ctrl);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1784

vlv_punit_write(display, PUNIT_REG_DSPSSPM, ctrl);

drivers/gpu/drm/i915/display/vlv_sideband.h

45

int vlv_punit_write(struct intel_display *display, u32 addr, u32 val);