drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

462

if (!bw_params->wm_table.entries[i].valid)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

465

ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

466

ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

679

bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

682

bw_params->wm_table.entries[i].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

686

bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

687

bw_params->wm_table.entries[i].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

745

rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

748

rn_bw_params.wm_table = lpddr4_wm_table_gs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

750

rn_bw_params.wm_table = lpddr4_wm_table_rn;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

754

rn_bw_params.wm_table = ddr4_wm_table_gs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

757

rn_bw_params.wm_table = ddr4_1R_wm_table_rn;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

759

rn_bw_params.wm_table = ddr4_wm_table_rn;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

33

extern struct wm_table ddr4_wm_table_gs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

34

extern struct wm_table lpddr4_wm_table_gs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

35

extern struct wm_table lpddr4_wm_table_with_disabled_ppt;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

36

extern struct wm_table ddr4_wm_table_rn;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

37

extern struct wm_table ddr4_1R_wm_table_rn;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

38

extern struct wm_table lpddr4_wm_table_rn;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

341

if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

342

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

343

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

344

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

345

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

347

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

394

if (!bw_params->wm_table.entries[i].valid)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

397

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

398

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

620

bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

623

bw_params->wm_table.entries[i].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

627

bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

628

bw_params->wm_table.entries[i].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

737

vg_bw_params.wm_table = lpddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

739

vg_bw_params.wm_table = ddr4_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

32

extern struct wm_table ddr4_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

33

extern struct wm_table lpddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

344

static struct wm_table ddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

381

static struct wm_table lpddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

430

if (!bw_params->wm_table.entries[i].valid)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

433

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

434

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

621

bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

624

bw_params->wm_table.entries[i].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

628

bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

629

bw_params->wm_table.entries[i].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

729

dcn31_bw_params.wm_table = lpddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

731

dcn31_bw_params.wm_table = ddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

410

static struct wm_table ddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

447

static struct wm_table lpddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

501

if (!bw_params->wm_table.entries[i].valid)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

504

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

505

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

749

bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

752

bw_params->wm_table.entries[i].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

756

bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

757

bw_params->wm_table.entries[i].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

846

dcn314_bw_params.wm_table = lpddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

848

dcn314_bw_params.wm_table = ddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

304

static struct wm_table ddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

341

static struct wm_table lpddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

390

if (!bw_params->wm_table.entries[i].valid)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

393

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

394

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

573

bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

576

bw_params->wm_table.entries[i].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

580

bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

581

bw_params->wm_table.entries[i].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

656

dcn315_bw_params.wm_table = lpddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

658

dcn315_bw_params.wm_table = ddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

270

static struct wm_table ddr4_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

307

static struct wm_table lpddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

356

if (!bw_params->wm_table.entries[i].valid)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

359

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

360

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

553

bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

556

bw_params->wm_table.entries[i].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

560

bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

561

bw_params->wm_table.entries[i].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

640

dcn316_bw_params.wm_table = lpddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

642

dcn316_bw_params.wm_table = ddr4_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

984

if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

986

table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1178

bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1181

bw_params->wm_table.entries[i].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1185

bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1186

bw_params->wm_table.entries[i].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1468

dcn35_bw_params.wm_table = lpddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1470

dcn35_bw_params.wm_table = ddr5_wm_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

763

static struct wm_table ddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

800

static struct wm_table lpddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

872

if (!bw_params->wm_table.entries[i].valid)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

875

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

876

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1317

if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1319

table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

189

clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

190

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

191

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

192

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

193

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

194

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

197

clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

202

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

203

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

204

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

205

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

206

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

207

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

209

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

213

clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2181

dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2188

dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2199

dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2294

table_entry = &bw_params->wm_table.entries[WM_D];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2302

table_entry = &bw_params->wm_table.entries[WM_C];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2307

table_entry = &bw_params->wm_table.entries[WM_B];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2313

table_entry = &bw_params->wm_table.entries[WM_A];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2468

bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2469

bw_params->wm_table.entries[WM_D].wm_inst = WM_D;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2470

bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2471

bw_params->wm_table.entries[WM_D].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

767

struct wm_table ddr4_wm_table_gs = {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

804

struct wm_table lpddr4_wm_table_gs = {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

841

struct wm_table lpddr4_wm_table_with_disabled_ppt = {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

878

struct wm_table ddr4_wm_table_rn = {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

915

struct wm_table ddr4_1R_wm_table_rn = {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

952

struct wm_table lpddr4_wm_table_rn = {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

294

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

297

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

298

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

299

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

341

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

361

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

366

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

367

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

368

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

408

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

436

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

437

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

516

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

669

base->bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

670

base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

671

base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

672

base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

673

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

674

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

675

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

676

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

677

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

691

base->bw_params->wm_table.nv_entries[WM_C].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

692

base->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

693

base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

694

base->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

695

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

696

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

697

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

698

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

699

base->bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

710

base->bw_params->wm_table.nv_entries[WM_D].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

711

base->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

712

base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

713

base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

714

base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

715

base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

716

base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

717

base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

718

base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

218

struct wm_table ddr4_wm_table = {

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

255

struct wm_table lpddr5_wm_table = {

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

443

table_entry = &bw_params->wm_table.entries[WM_D];

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

451

table_entry = &bw_params->wm_table.entries[WM_C];

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

456

table_entry = &bw_params->wm_table.entries[WM_B];

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

462

table_entry = &bw_params->wm_table.entries[WM_A];

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

458

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

459

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

460

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

461

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

469

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

474

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

476

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

478

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

203

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

205

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

211

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

212

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

213

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

214

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

215

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

216

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

217

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

218

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

219

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

220

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

223

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

224

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

225

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

226

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

227

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

228

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

229

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

230

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

231

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2347

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

236

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

237

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

238

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2385

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

239

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

240

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

241

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2415

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

242

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

243

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2439

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

244

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2440

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2441

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2442

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2443

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

245

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2508

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2536

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2537

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2538

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2556

if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

257

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2576

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2577

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2578

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

258

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

259

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

260

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

261

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

262

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2626

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

263

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2631

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

264

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

265

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

266

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

267

struct wm_table wm_table;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4830

Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4835

result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2581

Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

2586

(uint8_t *)wm_table, TABLE_WATERMARKS, false);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3709

Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

3714

(uint8_t *)wm_table, TABLE_WATERMARKS, false);