drivers/gpu/drm/i915/display/i9xx_wm.c

123

val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2);

drivers/gpu/drm/i915/display/i9xx_wm.c

132

ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2),

drivers/gpu/drm/i915/display/i9xx_wm.c

148

val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/i9xx_wm.c

3920

val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/i9xx_wm.c

3933

val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2);

drivers/gpu/drm/i915/display/i9xx_wm.c

3937

ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2),

drivers/gpu/drm/i915/display/i9xx_wm.c

3946

val = vlv_punit_read(display, PUNIT_REG_DDR_SETUP2);

drivers/gpu/drm/i915/display/intel_cdclk.c

617

val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_cdclk.c

699

val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_cdclk.c

704

ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM),

drivers/gpu/drm/i915/display/intel_cdclk.c

784

val = vlv_punit_read(display, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_cdclk.c

789

ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM),

drivers/gpu/drm/i915/display/intel_display_power.c

1892

ret = (vlv_punit_read(display, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1193

val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1197

ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1202

ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1209

vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1241

state = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS) & mask;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1255

ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL) & mask;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1744

state = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1757

ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1778

ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM);

drivers/gpu/drm/i915/display/intel_display_power_well.c

1786

ret = poll_timeout_us(ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM),

drivers/gpu/drm/i915/display/intel_display_power_well.c

1793

vlv_punit_read(display, PUNIT_REG_DSPSSPM));

drivers/gpu/drm/i915/display/intel_dram.c

125

val = vlv_punit_read(display, PUNIT_REG_GPU_FREQ_STS);

drivers/gpu/drm/i915/display/vlv_sideband.h

44

u32 vlv_punit_read(struct intel_display *display, u32 addr);