drivers/gpu/drm/i915/display/intel_cdclk.c

717

val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL);

drivers/gpu/drm/i915/display/intel_cdclk.c

722

ret = poll_timeout_us(val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL),

drivers/gpu/drm/i915/display/intel_dram.c

109

val = vlv_cck_read(display, CCK_FUSE_REG);

drivers/gpu/drm/i915/display/vlv_clock.c

27

hpll_freq = vlv_cck_read(display, CCK_FUSE_REG) &

drivers/gpu/drm/i915/display/vlv_clock.c

47

val = vlv_cck_read(display, reg);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

236

ret = poll_timeout_us(val = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL),

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

258

tmp = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

337

pll_ctl = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

338

pll_div = vlv_cck_read(display, CCK_REG_DSI_PLL_DIVIDER);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

607

cur_state = vlv_cck_read(display, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;

drivers/gpu/drm/i915/display/vlv_sideband.h

20

u32 vlv_cck_read(struct intel_display *display, u32 reg);