wlapi_bmac_write_shm
wlapi_bmac_write_shm(pi->sh->physhim, M_CURCHANNEL, m_cur_channel);
wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63);
wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N,
wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_TARGET,
wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_CUR,
wlapi_bmac_write_shm(pi->sh->physhim, offset + 6,
wlapi_bmac_write_shm(pi->sh->physhim, offset + 14,
wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET,
wlapi_bmac_write_shm(pi->sh->physhim, M_JSSI_0, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ, tx_comp.a0);
wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 2, tx_comp.b0);
wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 4, tx_comp.a1);
wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 6, tx_comp.b1);
wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX1, 0xFFFF);
wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX2, 0xFFFF);
wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION,
void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v);