wl1251_reg_read32
init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
acx_intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
wl1251_reg_read32(wl, CHIP_ID_B));
boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
tmp = wl1251_reg_read32(wl, SCR_PAD2);
tmp = wl1251_reg_read32(wl, SCR_PAD3);
boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
wl->mbox_ptr[0] = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
u32 wl1251_reg_read32(struct wl1251 *wl, int addr);
if (!(wl1251_reg_read32(wl, EE_CTL) & EE_CTL_READ))
*data = wl1251_reg_read32(wl, EE_DATA);
wl->chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR);
intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR);