wl1251_reg_write32
wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
wl1251_reg_write32(wl, 0x003058d4, 0x50);
wl1251_reg_write32(wl, 0x00305948, 0x11c001);
wl1251_reg_write32(wl, 0x003058f4, 0x1e);
wl1251_reg_write32(wl, 0x00305840, tmp);
wl1251_reg_write32(wl, 0x00305844, tmp);
wl1251_reg_write32(wl, 0x00305848, 0x3039);
wl1251_reg_write32(wl, 0x00305854, tmp);
wl1251_reg_write32(wl, 0x00305858, tmp);
wl1251_reg_write32(wl, 0x003058f8, tmp);
wl1251_reg_write32(wl, 0x003058f0, 0x29);
wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);
wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
wl1251_reg_write32(wl, ENABLE, 0x0);
wl1251_reg_write32(wl, SPARE_A2, 0xffff);
wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_CMD);
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK);
void wl1251_reg_write32(struct wl1251 *wl, int addr, u32 val);
wl1251_reg_write32(wl, EE_ADDR, offset);
wl1251_reg_write32(wl, EE_CTL, EE_CTL_READ);
wl1251_reg_write32(wl, EE_START, 0);
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1251_ACX_INTR_ALL);
wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
wl1251_reg_write32(wl, addr, data);
wl1251_reg_write32(wl, addr, data);