drivers/clk/meson/vid-pll-div.c

41

static const struct vid_pll_div vid_pll_div_table[] = {

drivers/clk/meson/vid-pll-div.c

61

static const struct vid_pll_div *_get_table_val(unsigned int shift_val,

drivers/clk/meson/vid-pll-div.c

80

const struct vid_pll_div *div;

drivers/gpu/drm/meson/meson_vclk.c

1127

params[freq].pll_od3, params[freq].vid_pll_div,

drivers/gpu/drm/meson/meson_vclk.c

371

unsigned int vid_pll_div;

drivers/gpu/drm/meson/meson_vclk.c

383

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

395

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

407

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

419

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

431

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

443

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

455

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

467

.vid_pll_div = VID_PLL_DIV_5,

drivers/gpu/drm/meson/meson_vclk.c

831

unsigned int vid_pll_div, unsigned int vclk_div,

drivers/gpu/drm/meson/meson_vclk.c

903

meson_vid_pll_set(priv, vid_pll_div);