wil_dbg_irq
wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",
wil_dbg_irq(wil, "mask_halp\n");
wil_dbg_irq(wil, "mask_irq_pseudo\n");
wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",
wil_dbg_irq(wil, "unmask_halp\n");
wil_dbg_irq(wil, "unmask_irq_pseudo\n");
wil_dbg_irq(wil, "mask_irq\n");
wil_dbg_irq(wil, "unmask_irq\n");
wil_dbg_irq(wil, "configure_interrupt_moderation\n");
wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",
wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
wil_dbg_irq(wil, "RX status ring\n");
wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
wil_dbg_irq(wil, "TX status ring\n");
wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
wil_dbg_irq(wil, "TX done\n");
wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
wil_dbg_irq(wil, "IRQ: FW ready\n");
wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");
wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
wil_dbg_irq(wil, "MBOX event\n");
wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
wil_dbg_irq(wil, "Thread IRQ\n");
wil_dbg_irq(wil, "set suspend_resp_comp to true\n");
wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
wil_dbg_irq(wil, "set_halp\n");
wil_dbg_irq(wil, "clear_halp\n");
wil_dbg_irq(wil, "halp_vote: start, HALP ref_cnt (%d)\n",
wil_dbg_irq(wil,
wil_dbg_irq(wil, "halp_vote: end, HALP ref_cnt (%d)\n",
wil_dbg_irq(wil, "halp_unvote: start, HALP ref_cnt (%d)\n",
wil_dbg_irq(wil, "HALP unvote\n");
wil_dbg_irq(wil, "halp_unvote:end, HALP ref_cnt (%d)\n",