drivers/gpu/drm/i915/gvt/cmd_parser.c

1408

stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1409

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

drivers/gpu/drm/i915/gvt/cmd_parser.c

1412

stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &

drivers/gpu/drm/i915/gvt/cmd_parser.c

1414

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1434

set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1437

set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1439

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1442

set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1444

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1449

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;

drivers/gpu/drm/i915/gvt/display.c

197

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

203

vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=

drivers/gpu/drm/i915/gvt/display.c

205

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

206

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

207

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

drivers/gpu/drm/i915/gvt/display.c

208

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

drivers/gpu/drm/i915/gvt/display.c

212

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=

drivers/gpu/drm/i915/gvt/display.c

216

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

221

vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=

drivers/gpu/drm/i915/gvt/display.c

223

vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=

drivers/gpu/drm/i915/gvt/display.c

227

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=

drivers/gpu/drm/i915/gvt/display.c

232

vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=

drivers/gpu/drm/i915/gvt/display.c

235

vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

237

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

239

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

241

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

244

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;

drivers/gpu/drm/i915/gvt/display.c

245

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;

drivers/gpu/drm/i915/gvt/display.c

247

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));

drivers/gpu/drm/i915/gvt/display.c

248

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/display.c

250

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/display.c

252

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);

drivers/gpu/drm/i915/gvt/display.c

253

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);

drivers/gpu/drm/i915/gvt/display.c

255

vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

256

vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

264

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

265

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

273

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

drivers/gpu/drm/i915/gvt/display.c

274

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

drivers/gpu/drm/i915/gvt/display.c

275

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

drivers/gpu/drm/i915/gvt/display.c

276

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

drivers/gpu/drm/i915/gvt/display.c

277

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

drivers/gpu/drm/i915/gvt/display.c

281

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);

drivers/gpu/drm/i915/gvt/display.c

282

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=

drivers/gpu/drm/i915/gvt/display.c

284

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=

drivers/gpu/drm/i915/gvt/display.c

286

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=

drivers/gpu/drm/i915/gvt/display.c

288

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=

drivers/gpu/drm/i915/gvt/display.c

291

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=

drivers/gpu/drm/i915/gvt/display.c

295

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=

drivers/gpu/drm/i915/gvt/display.c

297

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=

drivers/gpu/drm/i915/gvt/display.c

299

vgpu_vreg_t(vgpu,

drivers/gpu/drm/i915/gvt/display.c

303

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

305

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

310

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

311

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);

drivers/gpu/drm/i915/gvt/display.c

312

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

314

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

316

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

318

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

321

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

325

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

327

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

329

vgpu_vreg_t(vgpu,

drivers/gpu/drm/i915/gvt/display.c

334

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

336

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

341

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

342

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);

drivers/gpu/drm/i915/gvt/display.c

343

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

345

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

347

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

349

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/display.c

352

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

356

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

358

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/display.c

360

vgpu_vreg_t(vgpu,

drivers/gpu/drm/i915/gvt/display.c

365

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

367

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

374

vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |

drivers/gpu/drm/i915/gvt/display.c

382

vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

drivers/gpu/drm/i915/gvt/display.c

384

vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=

drivers/gpu/drm/i915/gvt/display.c

397

vgpu_vreg_t(vgpu, DPLL_CTRL1) =

drivers/gpu/drm/i915/gvt/display.c

399

vgpu_vreg_t(vgpu, DPLL_CTRL1) |=

drivers/gpu/drm/i915/gvt/display.c

401

vgpu_vreg_t(vgpu, LCPLL1_CTL) =

drivers/gpu/drm/i915/gvt/display.c

403

vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);

drivers/gpu/drm/i915/gvt/display.c

410

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

drivers/gpu/drm/i915/gvt/display.c

411

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

drivers/gpu/drm/i915/gvt/display.c

412

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

drivers/gpu/drm/i915/gvt/display.c

413

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

drivers/gpu/drm/i915/gvt/display.c

414

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

drivers/gpu/drm/i915/gvt/display.c

418

vgpu_vreg_t(vgpu, DPLL_CTRL2) &=

drivers/gpu/drm/i915/gvt/display.c

420

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

422

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

424

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

425

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

428

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

433

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

435

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

438

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

439

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

440

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

444

vgpu_vreg_t(vgpu, DPLL_CTRL2) &=

drivers/gpu/drm/i915/gvt/display.c

446

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

448

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

450

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

451

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

454

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

459

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/display.c

461

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

464

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

465

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

466

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

470

vgpu_vreg_t(vgpu, DPLL_CTRL2) &=

drivers/gpu/drm/i915/gvt/display.c

472

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

474

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

476

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

477

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

480

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

485

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=

drivers/gpu/drm/i915/gvt/display.c

487

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=

drivers/gpu/drm/i915/gvt/display.c

490

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

491

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

492

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

500

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

drivers/gpu/drm/i915/gvt/display.c

505

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

508

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;

drivers/gpu/drm/i915/gvt/display.c

510

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

515

vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;

drivers/gpu/drm/i915/gvt/display.c

519

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

520

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

521

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

drivers/gpu/drm/i915/gvt/display.c

522

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

drivers/gpu/drm/i915/gvt/display.c

525

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

662

vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/display.c

697

vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

drivers/gpu/drm/i915/gvt/display.c

699

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

701

vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

drivers/gpu/drm/i915/gvt/display.c

703

vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

705

vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

706

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

712

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

715

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

718

vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

drivers/gpu/drm/i915/gvt/display.c

720

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

722

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

728

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

730

vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

drivers/gpu/drm/i915/gvt/display.c

733

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

735

vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

drivers/gpu/drm/i915/gvt/display.c

738

vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

drivers/gpu/drm/i915/gvt/display.c

740

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

742

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

748

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

750

vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

drivers/gpu/drm/i915/gvt/display.c

753

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

755

vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

drivers/gpu/drm/i915/gvt/display.c

758

vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

drivers/gpu/drm/i915/gvt/display.c

760

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

762

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

77

if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))

drivers/gpu/drm/i915/gvt/display.c

94

if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)

drivers/gpu/drm/i915/gvt/edid.c

136

vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;

drivers/gpu/drm/i915/gvt/edid.c

138

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

drivers/gpu/drm/i915/gvt/edid.c

170

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

drivers/gpu/drm/i915/gvt/edid.c

171

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;

drivers/gpu/drm/i915/gvt/edid.c

177

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;

drivers/gpu/drm/i915/gvt/edid.c

179

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

drivers/gpu/drm/i915/gvt/edid.c

206

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;

drivers/gpu/drm/i915/gvt/edid.c

207

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;

drivers/gpu/drm/i915/gvt/edid.c

255

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

drivers/gpu/drm/i915/gvt/edid.c

267

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;

drivers/gpu/drm/i915/gvt/edid.c

305

if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {

drivers/gpu/drm/i915/gvt/fb_decoder.c

161

u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;

drivers/gpu/drm/i915/gvt/fb_decoder.c

224

val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

258

plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;

drivers/gpu/drm/i915/gvt/fb_decoder.c

274

plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>

drivers/gpu/drm/i915/gvt/fb_decoder.c

277

plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &

drivers/gpu/drm/i915/gvt/fb_decoder.c

281

val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

356

val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

382

plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;

drivers/gpu/drm/i915/gvt/fb_decoder.c

393

val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

399

plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));

drivers/gpu/drm/i915/gvt/fb_decoder.c

400

plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));

drivers/gpu/drm/i915/gvt/gtt.c

996

u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &

drivers/gpu/drm/i915/gvt/handlers.c

1038

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1040

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/handlers.c

1042

if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)

drivers/gpu/drm/i915/gvt/handlers.c

1060

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1062

if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)

drivers/gpu/drm/i915/gvt/handlers.c

1082

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1083

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/handlers.c

1085

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1423

if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRRD) {

drivers/gpu/drm/i915/gvt/handlers.c

1426

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

drivers/gpu/drm/i915/gvt/handlers.c

1450

if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRWR) {

drivers/gpu/drm/i915/gvt/handlers.c

1453

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

drivers/gpu/drm/i915/gvt/handlers.c

1455

write_virtual_sbi_register(vgpu, sbi_offset, vgpu_vreg_t(vgpu, SBI_DATA));

drivers/gpu/drm/i915/gvt/handlers.c

1709

u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);

drivers/gpu/drm/i915/gvt/handlers.c

1905

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/handlers.c

1907

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/handlers.c

1912

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/handlers.c

1914

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=

drivers/gpu/drm/i915/gvt/handlers.c

370

vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;

drivers/gpu/drm/i915/gvt/handlers.c

402

vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;

drivers/gpu/drm/i915/gvt/handlers.c

403

vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;

drivers/gpu/drm/i915/gvt/handlers.c

404

vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;

drivers/gpu/drm/i915/gvt/handlers.c

405

vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;

drivers/gpu/drm/i915/gvt/handlers.c

408

vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=

drivers/gpu/drm/i915/gvt/handlers.c

487

u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));

drivers/gpu/drm/i915/gvt/handlers.c

501

switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {

drivers/gpu/drm/i915/gvt/handlers.c

513

vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));

drivers/gpu/drm/i915/gvt/handlers.c

525

wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));

drivers/gpu/drm/i915/gvt/handlers.c

527

wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));

drivers/gpu/drm/i915/gvt/handlers.c

551

vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));

drivers/gpu/drm/i915/gvt/handlers.c

587

temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));

drivers/gpu/drm/i915/gvt/handlers.c

595

m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;

drivers/gpu/drm/i915/gvt/handlers.c

596

if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)

drivers/gpu/drm/i915/gvt/handlers.c

597

m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));

drivers/gpu/drm/i915/gvt/handlers.c

598

n = REG_FIELD_GET(PORT_PLL_N_MASK, vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));

drivers/gpu/drm/i915/gvt/handlers.c

599

p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));

drivers/gpu/drm/i915/gvt/handlers.c

600

p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));

drivers/gpu/drm/i915/gvt/handlers.c

624

if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&

drivers/gpu/drm/i915/gvt/handlers.c

625

(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {

drivers/gpu/drm/i915/gvt/handlers.c

626

dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &

drivers/gpu/drm/i915/gvt/handlers.c

636

switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &

drivers/gpu/drm/i915/gvt/handlers.c

674

port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &

drivers/gpu/drm/i915/gvt/handlers.c

690

link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));

drivers/gpu/drm/i915/gvt/handlers.c

691

link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));

drivers/gpu/drm/i915/gvt/handlers.c

694

htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);

drivers/gpu/drm/i915/gvt/handlers.c

695

vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);

drivers/gpu/drm/i915/gvt/handlers.c

823

vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))

drivers/gpu/drm/i915/gvt/handlers.c

841

u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));

drivers/gpu/drm/i915/gvt/handlers.c

843

u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));

drivers/gpu/drm/i915/gvt/handlers.c

884

if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)

drivers/gpu/drm/i915/gvt/handlers.c

887

if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)

drivers/gpu/drm/i915/gvt/handlers.c

889

&& ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)

drivers/gpu/drm/i915/gvt/handlers.c

947

vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

953

vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

957

vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=

drivers/gpu/drm/i915/gvt/handlers.c

978

vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);

drivers/gpu/drm/i915/gvt/mmio.c

260

vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;

drivers/gpu/drm/i915/gvt/mmio.c

263

vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;

drivers/gpu/drm/i915/gvt/mmio.c

266

vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;

drivers/gpu/drm/i915/gvt/mmio.c

269

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=

drivers/gpu/drm/i915/gvt/mmio.c

271

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/mmio.c

273

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/mmio.c

275

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/mmio.c

277

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/mmio.c

279

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=

drivers/gpu/drm/i915/gvt/mmio.c

281

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=

drivers/gpu/drm/i915/gvt/mmio.c

284

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/mmio.c

286

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/mmio.c

289

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/mmio.c

291

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/mmio.c

294

vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=

drivers/gpu/drm/i915/gvt/mmio_context.c

242

*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);

drivers/gpu/drm/i915/gvt/mmio_context.c

272

*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));

drivers/gpu/drm/i915/gvt/mmio_context.c

299

*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));

drivers/gpu/drm/i915/gvt/mmio_context.c

405

vgpu_vreg_t(vgpu, reg) = 0;

drivers/gpu/drm/i915/gvt/mmio_context.c

439

old_v = vgpu_vreg_t(pre, offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

443

new_v = vgpu_vreg_t(next, offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

457

old_v = vgpu_vreg_t(pre, l3_offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

461

new_v = vgpu_vreg_t(next, l3_offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

512

vgpu_vreg_t(pre, mmio->reg) =

drivers/gpu/drm/i915/gvt/mmio_context.c

515

vgpu_vreg_t(pre, mmio->reg) &=

drivers/gpu/drm/i915/gvt/mmio_context.c

517

old_v = vgpu_vreg_t(pre, mmio->reg);

drivers/gpu/drm/i915/gvt/mmio_context.c

536

new_v = vgpu_vreg_t(next, mmio->reg) |

drivers/gpu/drm/i915/gvt/mmio_context.c

539

new_v = vgpu_vreg_t(next, mmio->reg);

drivers/gpu/drm/i915/gvt/scheduler.c

661

vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =

drivers/gpu/drm/i915/gvt/scheduler.c

980

vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;

drivers/gpu/drm/i915/gvt/scheduler.c

981

vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;

drivers/gpu/drm/i915/gvt/vgpu.c

48

vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;

drivers/gpu/drm/i915/gvt/vgpu.c

49

vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;

drivers/gpu/drm/i915/gvt/vgpu.c

50

vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;

drivers/gpu/drm/i915/gvt/vgpu.c

51

vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;

drivers/gpu/drm/i915/gvt/vgpu.c

53

vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;

drivers/gpu/drm/i915/gvt/vgpu.c

54

vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;

drivers/gpu/drm/i915/gvt/vgpu.c

55

vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;

drivers/gpu/drm/i915/gvt/vgpu.c

57

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =

drivers/gpu/drm/i915/gvt/vgpu.c

59

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =

drivers/gpu/drm/i915/gvt/vgpu.c

61

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =

drivers/gpu/drm/i915/gvt/vgpu.c

63

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =

drivers/gpu/drm/i915/gvt/vgpu.c

66

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);

drivers/gpu/drm/i915/gvt/vgpu.c

68

vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;

drivers/gpu/drm/i915/gvt/vgpu.c

69

vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;