drivers/gpu/drm/i915/gvt/cmd_parser.c

1034

vgpu_vreg(vgpu, offset) = data;

drivers/gpu/drm/i915/gvt/cmd_parser.c

962

vreg = &vgpu_vreg(s->vgpu, offset);

drivers/gpu/drm/i915/gvt/debugfs.c

68

vreg = vgpu_vreg(param->vgpu, offset);

drivers/gpu/drm/i915/gvt/display.c

54

u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);

drivers/gpu/drm/i915/gvt/display.c

80

if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))

drivers/gpu/drm/i915/gvt/edid.c

149

memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);

drivers/gpu/drm/i915/gvt/edid.c

151

pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;

drivers/gpu/drm/i915/gvt/edid.c

190

if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {

drivers/gpu/drm/i915/gvt/edid.c

192

vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;

drivers/gpu/drm/i915/gvt/edid.c

245

if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))

drivers/gpu/drm/i915/gvt/edid.c

279

vgpu_vreg(vgpu, offset) = wvalue;

drivers/gpu/drm/i915/gvt/edid.c

307

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

318

memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);

drivers/gpu/drm/i915/gvt/edid.c

319

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

340

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

349

u32 value = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/edid.c

351

if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))

drivers/gpu/drm/i915/gvt/edid.c

352

vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;

drivers/gpu/drm/i915/gvt/edid.c

363

vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;

drivers/gpu/drm/i915/gvt/edid.c

394

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

428

memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);

drivers/gpu/drm/i915/gvt/edid.c

495

vgpu_vreg(vgpu, offset) = value;

drivers/gpu/drm/i915/gvt/edid.c

502

msg = vgpu_vreg(vgpu, offset + 4);

drivers/gpu/drm/i915/gvt/edid.c

513

vgpu_vreg(vgpu, offset) =

drivers/gpu/drm/i915/gvt/edid.c

560

vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;

drivers/gpu/drm/i915/gvt/execlist.c

117

vgpu_vreg(vgpu, status_reg) = status.ldw;

drivers/gpu/drm/i915/gvt/execlist.c

118

vgpu_vreg(vgpu, status_reg + 4) = status.udw;

drivers/gpu/drm/i915/gvt/execlist.c

139

ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);

drivers/gpu/drm/i915/gvt/execlist.c

152

vgpu_vreg(vgpu, offset) = status->ldw;

drivers/gpu/drm/i915/gvt/execlist.c

153

vgpu_vreg(vgpu, offset + 4) = status->udw;

drivers/gpu/drm/i915/gvt/execlist.c

156

vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;

drivers/gpu/drm/i915/gvt/execlist.c

262

status.ldw = vgpu_vreg(vgpu, status_reg);

drivers/gpu/drm/i915/gvt/execlist.c

263

status.udw = vgpu_vreg(vgpu, status_reg + 4);

drivers/gpu/drm/i915/gvt/execlist.c

516

ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);

drivers/gpu/drm/i915/gvt/execlist.c

519

vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;

drivers/gpu/drm/i915/gvt/execlist.c

98

status.ldw = vgpu_vreg(vgpu, status_reg);

drivers/gpu/drm/i915/gvt/execlist.c

99

status.udw = vgpu_vreg(vgpu, status_reg + 4);

drivers/gpu/drm/i915/gvt/handlers.c

1004

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1007

vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;

drivers/gpu/drm/i915/gvt/handlers.c

1017

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1020

vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;

drivers/gpu/drm/i915/gvt/handlers.c

1022

vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;

drivers/gpu/drm/i915/gvt/handlers.c

1038

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1060

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1082

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1085

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1088

if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)

drivers/gpu/drm/i915/gvt/handlers.c

113

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/handlers.c

1138

vgpu_vreg(vgpu, reg) = value;

drivers/gpu/drm/i915/gvt/handlers.c

119

memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);

drivers/gpu/drm/i915/gvt/handlers.c

1202

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1218

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1226

msg = vgpu_vreg(vgpu, offset + 4);

drivers/gpu/drm/i915/gvt/handlers.c

1246

vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;

drivers/gpu/drm/i915/gvt/handlers.c

1263

u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);

drivers/gpu/drm/i915/gvt/handlers.c

1285

vgpu_vreg(vgpu, offset + 4) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1304

vgpu_vreg(vgpu, offset + 4) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1305

vgpu_vreg(vgpu, offset + 8) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1306

vgpu_vreg(vgpu, offset + 12) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1307

vgpu_vreg(vgpu, offset + 16) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1308

vgpu_vreg(vgpu, offset + 20) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1317

vgpu_vreg(vgpu, offset + 4 * idx) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1339

vgpu_vreg(vgpu, offset +

drivers/gpu/drm/i915/gvt/handlers.c

1372

vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;

drivers/gpu/drm/i915/gvt/handlers.c

1428

vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, sbi_offset);

drivers/gpu/drm/i915/gvt/handlers.c

1440

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1448

vgpu_vreg(vgpu, offset) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1606

if (vgpu_vreg(vgpu, offset) &

drivers/gpu/drm/i915/gvt/handlers.c

1608

vgpu_vreg(vgpu, offset) |=

drivers/gpu/drm/i915/gvt/handlers.c

1611

vgpu_vreg(vgpu, offset) &=

drivers/gpu/drm/i915/gvt/handlers.c

1621

if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)

drivers/gpu/drm/i915/gvt/handlers.c

1622

vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;

drivers/gpu/drm/i915/gvt/handlers.c

1624

vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;

drivers/gpu/drm/i915/gvt/handlers.c

1634

if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)

drivers/gpu/drm/i915/gvt/handlers.c

1635

vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;

drivers/gpu/drm/i915/gvt/handlers.c

1646

mode = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1687

if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1690

if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1693

if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1696

if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1699

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1817

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1830

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1843

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1856

vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1859

vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1860

vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1864

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1872

u32 v = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1876

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1887

vgpu_vreg(vgpu, offset - 0x600) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1888

vgpu_vreg(vgpu, offset - 0x800) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1890

vgpu_vreg(vgpu, offset - 0x400) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1891

vgpu_vreg(vgpu, offset - 0x600) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1894

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1919

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1927

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1954

vgpu_vreg(vgpu, offset) = lower_32_bits(pat);

drivers/gpu/drm/i915/gvt/handlers.c

1965

vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;

drivers/gpu/drm/i915/gvt/handlers.c

1990

vgpu_vreg(vgpu, offset) =

drivers/gpu/drm/i915/gvt/handlers.c

2105

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

2137

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

2144

vgpu_vreg(vgpu, offset) = data;

drivers/gpu/drm/i915/gvt/handlers.c

307

old = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

3123

old_vreg = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

3125

mask = vgpu_vreg(vgpu, offset) >> 16;

drivers/gpu/drm/i915/gvt/handlers.c

3126

vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |

drivers/gpu/drm/i915/gvt/handlers.c

3127

(vgpu_vreg(vgpu, offset) & mask);

drivers/gpu/drm/i915/gvt/handlers.c

3184

old_vreg = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

3196

data |= vgpu_vreg(vgpu, offset) & ro_mask;

drivers/gpu/drm/i915/gvt/handlers.c

3202

u32 mask = vgpu_vreg(vgpu, offset) >> 16;

drivers/gpu/drm/i915/gvt/handlers.c

3204

vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)

drivers/gpu/drm/i915/gvt/handlers.c

3205

| (vgpu_vreg(vgpu, offset) & mask);

drivers/gpu/drm/i915/gvt/handlers.c

3238

intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));

drivers/gpu/drm/i915/gvt/handlers.c

330

vgpu_vreg(vgpu, offset) = new;

drivers/gpu/drm/i915/gvt/handlers.c

331

vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));

drivers/gpu/drm/i915/gvt/handlers.c

342

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

379

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

401

if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {

drivers/gpu/drm/i915/gvt/handlers.c

419

if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)

drivers/gpu/drm/i915/gvt/handlers.c

420

vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

422

vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

431

if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)

drivers/gpu/drm/i915/gvt/handlers.c

432

vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

434

vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

436

if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)

drivers/gpu/drm/i915/gvt/handlers.c

437

vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;

drivers/gpu/drm/i915/gvt/handlers.c

439

vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;

drivers/gpu/drm/i915/gvt/handlers.c

452

vgpu_vreg(vgpu, offset) = 1 << 17;

drivers/gpu/drm/i915/gvt/handlers.c

455

vgpu_vreg(vgpu, offset) = 0x3;

drivers/gpu/drm/i915/gvt/handlers.c

458

vgpu_vreg(vgpu, offset) = 0x2f << 16;

drivers/gpu/drm/i915/gvt/handlers.c

723

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

726

vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

730

vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

818

if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {

drivers/gpu/drm/i915/gvt/handlers.c

819

vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/handlers.c

821

vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/handlers.c

832

vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;

drivers/gpu/drm/i915/gvt/handlers.c

842

u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);

drivers/gpu/drm/i915/gvt/handlers.c

975

data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;

drivers/gpu/drm/i915/gvt/handlers.c

992

vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |

drivers/gpu/drm/i915/gvt/handlers.c

993

(vgpu_vreg(vgpu, offset) & sticky_mask);

drivers/gpu/drm/i915/gvt/handlers.c

994

vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);

drivers/gpu/drm/i915/gvt/interrupt.c

206

trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),

drivers/gpu/drm/i915/gvt/interrupt.c

207

(vgpu_vreg(vgpu, reg) ^ imr));

drivers/gpu/drm/i915/gvt/interrupt.c

209

vgpu_vreg(vgpu, reg) = imr;

drivers/gpu/drm/i915/gvt/interrupt.c

235

u32 virtual_ier = vgpu_vreg(vgpu, reg);

drivers/gpu/drm/i915/gvt/interrupt.c

247

vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;

drivers/gpu/drm/i915/gvt/interrupt.c

248

vgpu_vreg(vgpu, reg) |= ier;

drivers/gpu/drm/i915/gvt/interrupt.c

277

trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),

drivers/gpu/drm/i915/gvt/interrupt.c

278

(vgpu_vreg(vgpu, reg) ^ ier));

drivers/gpu/drm/i915/gvt/interrupt.c

280

vgpu_vreg(vgpu, reg) = ier;

drivers/gpu/drm/i915/gvt/interrupt.c

315

trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),

drivers/gpu/drm/i915/gvt/interrupt.c

316

(vgpu_vreg(vgpu, reg) ^ iir));

drivers/gpu/drm/i915/gvt/interrupt.c

321

vgpu_vreg(vgpu, reg) &= ~iir;

drivers/gpu/drm/i915/gvt/interrupt.c

355

u32 val = vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

357

& vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

387

vgpu_vreg(vgpu, isr) &= ~clear_bits;

drivers/gpu/drm/i915/gvt/interrupt.c

388

vgpu_vreg(vgpu, isr) |= set_bits;

drivers/gpu/drm/i915/gvt/interrupt.c

395

vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));

drivers/gpu/drm/i915/gvt/interrupt.c

477

if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

480

set_bit(bit, (void *)&vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

532

if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &

drivers/gpu/drm/i915/gvt/interrupt.c

544

if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))

drivers/gpu/drm/i915/gvt/interrupt.c

545

& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))

drivers/gpu/drm/i915/gvt/interrupt.c

549

if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))

drivers/gpu/drm/i915/gvt/scheduler.c

282

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

drivers/gpu/drm/i915/gvt/scheduler.c

286

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

drivers/gpu/drm/i915/gvt/scheduler.c

290

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =