wait_for
ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
err = wait_for(intel_uncore_read_fw(gt->uncore,
ret = wait_for(done, slow_timeout_ms);
if (wait_for(READ_ONCE(*map), 10)) {
if (wait_for(!list_empty(&rq->fence.cb_list), 10)) {
wait_for(i915_seqno_passed(hws_seqno(h, rq),
return wait_for(intel_engine_is_idle(engine), IGT_IDLE_TIMEOUT) == 0;
if (wait_for(!intel_rps_set(rps, freq), 50)) {
if (wait_for(intel_uncore_read_fw(gt->uncore,
if (wait_for(intel_uncore_read(engine->uncore, CS_GPR(0)),
if (wait_for(READ_ONCE(*cntr), 10)) {
if (wait_for(i915_request_completed(rq), HZ / 2)) {
err = wait_for(*marker != 0, 300);
err = wait_for(gsc->proxy.component, GSC_PROXY_INIT_TIMEOUT_MS);
if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS))
if (wait_for(i915_request_started(rq), GSC_HECI_REPLY_LATENCY_MS))
ret = wait_for(done, 1000);
err = wait_for(done, GUC_CTB_RESPONSE_TIMEOUT_LONG_MS);
ret = wait_for(guc_load_done(uncore, &status, &success), 1000);
if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
if (wait_for(context_close_done(ce), 1500))
ret = wait_for(gt->uc.guc.fast_response_selftest != 1 || i915_request_completed(rq),
wait_for(intel_engines_are_idle(gt), 200))
if (wait_for(COND, 2000) == -ETIMEDOUT) {
ret = wait_for(done, slow_timeout_ms);
if (wait_for(pxp_fw_dependencies_completed(pxp), timeout_ms))
if (wait_for(READ_ONCE(*sema) == 0, 50)) {
if (wait_for(READ_ONCE(*sema) == 0, 50)) {
if (i > 1 && wait_for(READ_ONCE(sema[i - 1]), 500)) {
wait_for(READ_ONCE(sema[i - 1]), 500);
if (wait_for(READ_ONCE(sema[2 * i]) == -1, 500)) {
if (wait_for(READ_ONCE(sema[2 * i - 2]) != -1, 500)) {
if (wait_for(READ_ONCE(sema[i]) == -1, 50)) {
if (need_to_wait && wait_for(!__gsc_proxy_init_progressing(&i915->media_gt->uc.gsc),
wait_for(i915_sw_fence_done(&huc->delayed_load.fence), timeout_ms))
wait_for(i915_seqno_passed(hws_seqno(spin, rq),
if (wait_for(readl(reg) == 0, 100)) {
ret = wait_for(((reg_value =
if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS),
if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) &
if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) &
ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) &
ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
host->wait_for = MMCIF_WAIT_FOR_STOP;
wait_work = host->wait_for;
host->state, host->wait_for);
if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
host->wait_for = MMCIF_WAIT_FOR_REQUEST;
host->wait_for, mrq->cmd->opcode);
switch (host->wait_for) {
host->wait_for = MMCIF_WAIT_FOR_REQUEST;
enum sh_mmcif_wait_for wait_for;
host->state, host->wait_for);
host->state, host->wait_for);
host->state, host->wait_for);
host->wait_for = MMCIF_WAIT_FOR_READ;
host->wait_for = MMCIF_WAIT_FOR_READ_END;
host->wait_for = MMCIF_WAIT_FOR_MREAD;
host->wait_for = MMCIF_WAIT_FOR_WRITE;
host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
host->wait_for = MMCIF_WAIT_FOR_MWRITE;
host->wait_for = MMCIF_WAIT_FOR_CMD;
unsigned long wait_for;
wait_for = (cmd->allowed + 1) * req->timeout;
if (time_before(cmd->jiffies_at_alloc + wait_for, jiffies)) {
wait_for/HZ);
struct fscache_cookie *wait_for)
enum fscache_cookie_state *statep = &wait_for->state;
wait_var_event_timeout(statep, fscache_cookie_is_dropped(wait_for),
if (!fscache_cookie_is_dropped(wait_for)) {
candidate->debug_id, wait_for->debug_id);
wait_var_event(statep, fscache_cookie_is_dropped(wait_for));
struct fscache_cookie *cursor, *wait_for = NULL;
wait_for = fscache_get_cookie(cursor,
if (wait_for) {
fscache_wait_on_collision(candidate, wait_for);
fscache_put_cookie(wait_for, fscache_cookie_put_hash_collision);
ssize_t wait_for, time_t sec)
wait_for--;
wait_for--;
} while (wait_for > 0);