drivers/gpu/drm/i915/gt/intel_workarounds.c

2241

wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2249

wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2256

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2293

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2305

wa_mcr_masked_en(wal,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2313

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2317

wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2798

wa_mcr_masked_en(wal,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2807

wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2810

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, XELPG_DISABLE_TDL_SVHS_GATING);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2819

wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2824

wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,

drivers/gpu/drm/i915/gt/intel_workarounds.c

2847

wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);

drivers/gpu/drm/i915/gt/intel_workarounds.c

371

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,

drivers/gpu/drm/i915/gt/intel_workarounds.c

418

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);

drivers/gpu/drm/i915/gt/intel_workarounds.c

425

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,

drivers/gpu/drm/i915/gt/intel_workarounds.c

428

wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,

drivers/gpu/drm/i915/gt/intel_workarounds.c

444

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);

drivers/gpu/drm/i915/gt/intel_workarounds.c

463

wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,

drivers/gpu/drm/i915/gt/intel_workarounds.c

469

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,

drivers/gpu/drm/i915/gt/intel_workarounds.c

475

wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,

drivers/gpu/drm/i915/gt/intel_workarounds.c

516

wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,

drivers/gpu/drm/i915/gt/intel_workarounds.c

520

wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);

drivers/gpu/drm/i915/gt/intel_workarounds.c

599

wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,

drivers/gpu/drm/i915/gt/intel_workarounds.c

620

wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,

drivers/gpu/drm/i915/gt/intel_workarounds.c

644

wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,

drivers/gpu/drm/i915/gt/intel_workarounds.c

663

wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);

drivers/gpu/drm/i915/gt/intel_workarounds.c

677

wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,

drivers/gpu/drm/i915/gt/intel_workarounds.c

687

wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);

drivers/gpu/drm/i915/gt/intel_workarounds.c

706

wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);

drivers/gpu/drm/i915/gt/intel_workarounds.c

798

wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,

drivers/gpu/drm/i915/gt/intel_workarounds.c

805

wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);

drivers/gpu/drm/i915/gt/intel_workarounds.c

811

wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);

drivers/gpu/drm/i915/gt/intel_workarounds.c

845

wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,

drivers/gpu/drm/i915/gt/intel_workarounds.c

849

wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);

drivers/gpu/drm/i915/gt/intel_workarounds.c

852

wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);

drivers/gpu/drm/i915/gt/intel_workarounds.c

859

wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);