drivers/gpu/drm/i915/gt/intel_workarounds.c

1130

wa_add(wal,

drivers/gpu/drm/i915/gt/intel_workarounds.c

1526

wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,

drivers/gpu/drm/i915/gt/intel_workarounds.c

1569

wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,

drivers/gpu/drm/i915/gt/intel_workarounds.c

248

wa_add(wal, reg, clear, set, clear | set, false);

drivers/gpu/drm/i915/gt/intel_workarounds.c

2663

wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2679

wa_add(wal, ECOSKPD(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

301

wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);

drivers/gpu/drm/i915/gt/intel_workarounds.c

313

wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);

drivers/gpu/drm/i915/gt/intel_workarounds.c

326

wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);

drivers/gpu/drm/i915/gt/intel_workarounds.c

757

wa_add(wal,

drivers/gpu/drm/i915/gt/intel_workarounds.c

828

wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);