w83781d_write_value
w83781d_write_value(data, W83781D_REG_CONFIG, 0x80);
w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
w83781d_write_value(data, W83781D_REG_PWMCLK12, p);
w83781d_write_value(data, W83781D_REG_BEEP_INTS2, 0);
w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
w83781d_write_value(data, W83781D_REG_TEMP2_CONFIG,
w83781d_write_value(data,
w83781d_write_value(data, W83781D_REG_CONFIG,
static int w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value);
w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \
w83781d_write_value(data, W83781D_REG_FAN_MIN(nr),
w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
w83781d_write_value(data, W83781D_REG_BEEP_INTS1,
w83781d_write_value(data, W83781D_REG_BEEP_INTS2,
w83781d_write_value(data, W83781D_REG_BEEP_INTS3,
w83781d_write_value(data, W83781D_REG_BEEP_INTS1, reg);
w83781d_write_value(data, W83781D_REG_BEEP_INTS2, reg);
w83781d_write_value(data, W83781D_REG_BEEP_INTS3, reg);
w83781d_write_value(data, nr == 2 ?
w83781d_write_value(data, W83781D_REG_VBAT, reg);
w83781d_write_value(data, W83781D_REG_FAN_MIN(nr), data->fan_min[nr]);
w83781d_write_value(data, W83781D_REG_PWM[nr], data->pwm[nr]);
w83781d_write_value(data, W83781D_REG_PWMCLK12,
w83781d_write_value(data, W83781D_REG_BEEP_CONFIG,
w83781d_write_value(data, W83781D_REG_SCFG1,
w83781d_write_value(data, W83781D_REG_SCFG2,
w83781d_write_value(data, W83781D_REG_SCFG1,
w83781d_write_value(data, W83781D_REG_SCFG2,
w83781d_write_value(data, W83781D_REG_SCFG1,
w83781d_write_value(data, W83781D_REG_I2C_SUBADDR,