vx_outl
vx_outl(chip, HIFREQ, (clock >> 8) & 0x0f);
vx_outl(chip, LOFREQ, clock & 0xff);
vx_outl(chip, CSUER, 1); /* read */
vx_outl(chip, RUER, index & XX_UER_CBITS_OFFSET_MASK);
vx_outl(chip, CSUER, 0); /* write */
vx_outl(chip, RUER, (val << 7) | (index & XX_UER_CBITS_OFFSET_MASK));
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
vx_outl(chip, CDSP, chip->regCDSP);
vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
vx_outl(chip, RESET_DMA, 0);
vx_outl(chip, ICR, 0);
vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
vx_outl(chip, STATUS, 0);
vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK);
vx_outl(chip, STATUS, 0);
vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK);
vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK);
vx_outl(chip, CDSP, chip->regCDSP);
vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
vx_outl(chip, CDSP, chip->regCDSP);
vx_outl(_chip, SELMIC, chip->regSELMIC);
vx_outl(chip, CFG, chip->regCFG);
vx_outl(chip, CFG, chip->regCFG);
vx_outl(chip, SELMIC, chip->regSELMIC);
vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0));