arch/alpha/include/asm/core_cia.h

428

return *(vulp)addr;

arch/alpha/include/asm/core_cia.h

436

*(vulp)addr = b;

arch/alpha/include/asm/core_mcpcia.h

346

return *(vulp)addr;

arch/alpha/include/asm/core_mcpcia.h

356

*(vulp)addr = b;

arch/alpha/include/asm/core_t2.h

400

return *(vulp) ((addr << 5) + T2_IO + 0x18);

arch/alpha/include/asm/core_t2.h

405

*(vulp) ((addr << 5) + T2_IO + 0x18) = b;

arch/alpha/include/asm/core_t2.h

603

#undef vulp

arch/alpha/kernel/core_cia.c

796

pyxis_cc = *(vulp)PYXIS_RT_COUNT;

arch/alpha/kernel/core_cia.c

797

do { } while(*(vulp)PYXIS_RT_COUNT - pyxis_cc < 4096);

arch/alpha/kernel/core_t2.c

192

t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;

arch/alpha/kernel/core_t2.c

193

*(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;

arch/alpha/kernel/core_t2.c

227

*(vulp)T2_HAE_3 = t2_cfg;

arch/alpha/kernel/core_t2.c

244

t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;

arch/alpha/kernel/core_t2.c

245

*(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;

arch/alpha/kernel/core_t2.c

278

*(vulp)T2_HAE_3 = t2_cfg;

arch/alpha/kernel/core_t2.c

334

*(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */

arch/alpha/kernel/core_t2.c

336

*(vulp)T2_WMASK1 = temp;

arch/alpha/kernel/core_t2.c

337

*(vulp)T2_TBASE1 = 0;

arch/alpha/kernel/core_t2.c

341

__func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);

arch/alpha/kernel/core_t2.c

358

*(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */

arch/alpha/kernel/core_t2.c

360

*(vulp)T2_WMASK2 = temp;

arch/alpha/kernel/core_t2.c

361

*(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;

arch/alpha/kernel/core_t2.c

368

__func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);

arch/alpha/kernel/core_t2.c

377

printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2);

arch/alpha/kernel/core_t2.c

378

printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3);

arch/alpha/kernel/core_t2.c

379

printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4);

arch/alpha/kernel/core_t2.c

380

printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE);

arch/alpha/kernel/core_t2.c

383

*(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);

arch/alpha/kernel/core_t2.c

385

*(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);

arch/alpha/kernel/core_t2.c

391

t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;

arch/alpha/kernel/core_t2.c

392

t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;

arch/alpha/kernel/core_t2.c

393

t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;

arch/alpha/kernel/core_t2.c

394

t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;

arch/alpha/kernel/core_t2.c

395

t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;

arch/alpha/kernel/core_t2.c

396

t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;

arch/alpha/kernel/core_t2.c

399

t2_saved_config.hae_2 = *(vulp)T2_HAE_2;

arch/alpha/kernel/core_t2.c

400

t2_saved_config.hae_3 = *(vulp)T2_HAE_3;

arch/alpha/kernel/core_t2.c

401

t2_saved_config.hae_4 = *(vulp)T2_HAE_4;

arch/alpha/kernel/core_t2.c

402

t2_saved_config.hbase = *(vulp)T2_HBASE;

arch/alpha/kernel/core_t2.c

421

temp = *(vulp)T2_IOCSR;

arch/alpha/kernel/core_t2.c

425

*(vulp)T2_IOCSR = temp | (0x1UL << 26);

arch/alpha/kernel/core_t2.c

427

*(vulp)T2_IOCSR; /* read it back to make sure */

arch/alpha/kernel/core_t2.c

463

*(vulp)T2_HBASE = 0x0; /* Disable HOLES. */

arch/alpha/kernel/core_t2.c

466

*(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */

arch/alpha/kernel/core_t2.c

467

*(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */

arch/alpha/kernel/core_t2.c

468

*(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */

arch/alpha/kernel/core_t2.c

479

*(vulp)T2_HAE_4 = 0; mb();

arch/alpha/kernel/core_t2.c

488

*(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;

arch/alpha/kernel/core_t2.c

489

*(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;

arch/alpha/kernel/core_t2.c

490

*(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;

arch/alpha/kernel/core_t2.c

491

*(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;

arch/alpha/kernel/core_t2.c

492

*(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;

arch/alpha/kernel/core_t2.c

493

*(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;

arch/alpha/kernel/core_t2.c

496

*(vulp)T2_HAE_1 = srm_hae;

arch/alpha/kernel/core_t2.c

497

*(vulp)T2_HAE_2 = t2_saved_config.hae_2;

arch/alpha/kernel/core_t2.c

498

*(vulp)T2_HAE_3 = t2_saved_config.hae_3;

arch/alpha/kernel/core_t2.c

499

*(vulp)T2_HAE_4 = t2_saved_config.hae_4;

arch/alpha/kernel/core_t2.c

500

*(vulp)T2_HBASE = t2_saved_config.hbase;

arch/alpha/kernel/core_t2.c

502

*(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */

arch/alpha/kernel/core_t2.c

510

t2_iocsr = *(vulp)T2_IOCSR;

arch/alpha/kernel/core_t2.c

513

*(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);

arch/alpha/kernel/core_t2.c

515

*(vulp)T2_IOCSR; /* read it back to make sure */

arch/alpha/kernel/core_t2.c

518

*(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);

arch/alpha/kernel/core_t2.c

520

*(vulp)T2_IOCSR; /* read it back to make sure */

arch/alpha/kernel/core_t2.c

540

*(vulp)T2_CERR1 |= *(vulp)T2_CERR1;

arch/alpha/kernel/core_t2.c

541

*(vulp)T2_PERR1 |= *(vulp)T2_PERR1;

arch/alpha/kernel/irq_pyxis.c

27

*(vulp)PYXIS_INT_MASK = mask;

arch/alpha/kernel/irq_pyxis.c

29

*(vulp)PYXIS_INT_MASK;

arch/alpha/kernel/irq_pyxis.c

51

*(vulp)PYXIS_INT_MASK = mask;

arch/alpha/kernel/irq_pyxis.c

54

*(vulp)PYXIS_INT_REQ = bit;

arch/alpha/kernel/irq_pyxis.c

57

*(vulp)PYXIS_INT_MASK;

arch/alpha/kernel/irq_pyxis.c

74

pld = *(vulp)PYXIS_INT_REQ;

arch/alpha/kernel/irq_pyxis.c

96

*(vulp)PYXIS_INT_MASK = 0; /* disable all */

arch/alpha/kernel/irq_pyxis.c

97

*(vulp)PYXIS_INT_REQ = -1; /* flush all */

arch/alpha/kernel/setup.c

1244

sc_ctl = *(vulp) phys_to_virt (0xfffff000a8UL);

arch/alpha/kernel/setup.c

1277

cbox_config = *(vulp) phys_to_virt (0xfffff00008UL);

arch/alpha/kernel/sys_miata.c

69

*(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */

arch/alpha/kernel/sys_miata.c

70

*(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */

arch/alpha/kernel/sys_ruffian.c

189

bank = *(vulp)bank_addr;

arch/alpha/kernel/sys_ruffian.c

39

*(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();

arch/alpha/kernel/sys_ruffian.c

40

*(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */