arch/alpha/include/asm/core_cia.h

374

*(vuip) ((addr << 5) + base_and_type) = w;

arch/alpha/include/asm/core_cia.h

404

*(vuip) ((addr << 5) + base_and_type) = w;

arch/alpha/include/asm/core_cia.h

412

return *(vuip)addr;

arch/alpha/include/asm/core_cia.h

420

*(vuip)addr = b;

arch/alpha/include/asm/core_mcpcia.h

292

*(vuip) ((addr << 5) + hose + 0x00) = w;

arch/alpha/include/asm/core_mcpcia.h

316

*(vuip) ((addr << 5) + hose + 0x08) = w;

arch/alpha/include/asm/core_mcpcia.h

326

return *(vuip)addr;

arch/alpha/include/asm/core_mcpcia.h

336

*(vuip)addr = b;

arch/alpha/include/asm/core_t2.h

368

*(vuip) ((addr << 5) + T2_IO + 0x00) = w;

arch/alpha/include/asm/core_t2.h

383

*(vuip) ((addr << 5) + T2_IO + 0x08) = w;

arch/alpha/include/asm/core_t2.h

389

return *(vuip) ((addr << 5) + T2_IO + 0x18);

arch/alpha/include/asm/core_t2.h

394

*(vuip) ((addr << 5) + T2_IO + 0x18) = b;

arch/alpha/include/asm/core_t2.h

475

result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);

arch/alpha/include/asm/core_t2.h

490

result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);

arch/alpha/include/asm/core_t2.h

502

r0 = *(vuip)(work);

arch/alpha/include/asm/core_t2.h

503

r1 = *(vuip)(work + (4 << 5));

arch/alpha/include/asm/core_t2.h

515

*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;

arch/alpha/include/asm/core_t2.h

526

*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;

arch/alpha/include/asm/core_t2.h

539

*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;

arch/alpha/include/asm/core_t2.h

550

*(vuip)work = b;

arch/alpha/include/asm/core_t2.h

551

*(vuip)(work + (4 << 5)) = b >> 32;

arch/alpha/include/asm/core_t2.h

602

#undef vuip

arch/alpha/kernel/core_irongate.c

120

*value = *(vuip)addr;

arch/alpha/kernel/core_irongate.c

149

*(vuip)addr = value;

arch/alpha/kernel/core_irongate.c

151

*(vuip)addr;

arch/alpha/kernel/core_marvel.c

1035

vuip addr;

arch/alpha/kernel/core_marvel.c

1041

addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0);

arch/alpha/kernel/core_marvel.c

552

*value = *(vuip)addr;

arch/alpha/kernel/core_marvel.c

582

*(vuip)addr = value;

arch/alpha/kernel/core_marvel.c

584

*(vuip)addr;

arch/alpha/kernel/core_mcpcia.c

102

stat0 = *(vuip)MCPCIA_CAP_ERR(mid);

arch/alpha/kernel/core_mcpcia.c

103

*(vuip)MCPCIA_CAP_ERR(mid) = stat0;

arch/alpha/kernel/core_mcpcia.c

105

*(vuip)MCPCIA_CAP_ERR(mid);

arch/alpha/kernel/core_mcpcia.c

116

value = *((vuip)addr);

arch/alpha/kernel/core_mcpcia.c

147

stat0 = *(vuip)MCPCIA_CAP_ERR(mid);

arch/alpha/kernel/core_mcpcia.c

148

*(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();

arch/alpha/kernel/core_mcpcia.c

149

*(vuip)MCPCIA_CAP_ERR(mid);

arch/alpha/kernel/core_mcpcia.c

158

*((vuip)addr) = value;

arch/alpha/kernel/core_mcpcia.c

161

*(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */

arch/alpha/kernel/core_mcpcia.c

249

*(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0;

arch/alpha/kernel/core_mcpcia.c

273

pci_rev = *(vuip)MCPCIA_REV(mid);

arch/alpha/kernel/core_mcpcia.c

337

*(vuip)MCPCIA_CAP_ERR(mid);

arch/alpha/kernel/core_mcpcia.c

338

*(vuip)MCPCIA_CAP_ERR(mid) = 0xffffffff; /* Clear them all. */

arch/alpha/kernel/core_mcpcia.c

340

*(vuip)MCPCIA_CAP_ERR(mid); /* Re-read for force write. */

arch/alpha/kernel/core_mcpcia.c

354

tmp = *(vuip)MCPCIA_CAP_ERR(mid);

arch/alpha/kernel/core_mcpcia.c

356

*(vuip)MCPCIA_CAP_ERR(mid) = tmp;

arch/alpha/kernel/core_mcpcia.c

358

tmp = *(vuip)MCPCIA_CAP_ERR(mid);

arch/alpha/kernel/core_mcpcia.c

376

*(vuip)MCPCIA_W0_BASE(mid) = hose->sg_isa->dma_base | 3;

arch/alpha/kernel/core_mcpcia.c

377

*(vuip)MCPCIA_W0_MASK(mid) = (hose->sg_isa->size - 1) & 0xfff00000;

arch/alpha/kernel/core_mcpcia.c

378

*(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8;

arch/alpha/kernel/core_mcpcia.c

380

*(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3;

arch/alpha/kernel/core_mcpcia.c

381

*(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000;

arch/alpha/kernel/core_mcpcia.c

382

*(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8;

arch/alpha/kernel/core_mcpcia.c

384

*(vuip)MCPCIA_W2_BASE(mid) = __direct_map_base | 1;

arch/alpha/kernel/core_mcpcia.c

385

*(vuip)MCPCIA_W2_MASK(mid) = (__direct_map_size - 1) & 0xfff00000;

arch/alpha/kernel/core_mcpcia.c

386

*(vuip)MCPCIA_T2_BASE(mid) = 0;

arch/alpha/kernel/core_mcpcia.c

388

*(vuip)MCPCIA_W3_BASE(mid) = 0x0;

arch/alpha/kernel/core_mcpcia.c

392

*(vuip)MCPCIA_HBASE(mid) = 0x0;

arch/alpha/kernel/core_mcpcia.c

395

*(vuip)MCPCIA_HAE_MEM(mid) = 0U;

arch/alpha/kernel/core_mcpcia.c

397

*(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */

arch/alpha/kernel/core_mcpcia.c

398

*(vuip)MCPCIA_HAE_IO(mid) = 0;

arch/alpha/kernel/core_mcpcia.c

400

*(vuip)MCPCIA_HAE_IO(mid); /* read it back. */

arch/alpha/kernel/core_polaris.c

101

*value = *(vuip)addr;

arch/alpha/kernel/core_polaris.c

131

*(vuip)addr = value;

arch/alpha/kernel/core_polaris.c

133

*(vuip)addr;

arch/alpha/kernel/core_t2.c

205

value = *(vuip)addr;

arch/alpha/kernel/core_t2.c

257

*(vuip)addr = value;

arch/alpha/kernel/core_titan.c

156

*value = *(vuip)addr;

arch/alpha/kernel/core_titan.c

185

*(vuip)addr = value;

arch/alpha/kernel/core_titan.c

187

*(vuip)addr;

arch/alpha/kernel/core_tsunami.c

133

*value = *(vuip)addr;

arch/alpha/kernel/core_tsunami.c

162

*(vuip)addr = value;

arch/alpha/kernel/core_tsunami.c

164

*(vuip)addr;

arch/alpha/kernel/core_wildfire.c

399

*value = *(vuip)addr;

arch/alpha/kernel/core_wildfire.c

428

*(vuip)addr = value;

arch/alpha/kernel/core_wildfire.c

430

*(vuip)addr;

arch/alpha/kernel/irq_i8259.c

125

int j = *(vuip) IACK_SC;

arch/alpha/kernel/irq_pyxis.c

101

*(vuip) CIA_IACK_SC;

arch/alpha/kernel/setup.c

1229

car = *(vuip) phys_to_virt (0x120000078UL);

arch/alpha/kernel/sys_alcor.c

116

*(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */

arch/alpha/kernel/sys_alcor.c

117

*(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */

arch/alpha/kernel/sys_alcor.c

118

*(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */

arch/alpha/kernel/sys_alcor.c

119

*(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */

arch/alpha/kernel/sys_alcor.c

213

*(vuip) GRU_RESET = 0x0000dead;

arch/alpha/kernel/sys_alcor.c

41

*(vuip)GRU_INT_MASK = mask;

arch/alpha/kernel/sys_alcor.c

63

*(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();

arch/alpha/kernel/sys_alcor.c

64

*(vuip)GRU_INT_CLEAR = 0; mb();

arch/alpha/kernel/sys_alcor.c

73

*(vuip)GRU_INT_CLEAR = 0x80000000; mb();

arch/alpha/kernel/sys_alcor.c

74

*(vuip)GRU_INT_CLEAR = 0; mb();

arch/alpha/kernel/sys_alcor.c

91

pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS;

arch/alpha/kernel/sys_miata.c

254

*(vuip) PYXIS_RESET = 0x0000dead;

arch/alpha/kernel/sys_rawhide.c

121

*(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1;

arch/alpha/kernel/sys_rawhide.c

177

*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask;

arch/alpha/kernel/sys_rawhide.c

178

*(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0;

arch/alpha/kernel/sys_rawhide.c

49

*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask;

arch/alpha/kernel/sys_rawhide.c

51

*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose));

arch/alpha/kernel/sys_ruffian.c

95

*(vuip) PYXIS_RESET = 0x0000dead;