vsc_write
vsc_write( adapter, ib[i].addr, ib[i].data );
vsc_write(adapter, REG_RAM_BIST_CMD, data);
vsc_write(adapter, REG_RAM_BIST_CMD, data);
vsc_write(adapter, REG_MEM_BIST, 0x5);
vsc_write(adapter, REG_DEV_SETUP(port), 0x0);
vsc_write(adapter, REG_SPI4_MISC, 0x00040409);
vsc_write(adapter, REG_SPI4_MISC, 0x60040400);
vsc_write(adapter, REG_DEV_SETUP(port), 0x1);
vsc_write(adapter, REG_MEM_BIST, 0x0);
vsc_write(mac->adapter, REG_MAC_LOW_ADDR(port),
vsc_write(mac->adapter, REG_MAC_HIGH_ADDR(port),
vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, val | (port << 28));
vsc_write(mac->adapter, REG_ING_FFILT_MASK0,
vsc_write(mac->adapter, REG_ING_FFILT_MASK1,
vsc_write(mac->adapter, REG_ING_FFILT_MASK2,
vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, v);
vsc_write(mac->adapter, REG_MAX_LEN(port), mtu + 14 + 4);
vsc_write(mac->adapter, REG_MODE_CFG(port), v);
vsc_write(mac->adapter, REG_DEV_SETUP(port), v | 1); /* reset */
vsc_write(mac->adapter, REG_DEV_SETUP(port), v);
vsc_write(mac->adapter, REG_DBG(port), v);
vsc_write(mac->adapter, REG_TX_IFG(port),
vsc_write(mac->adapter, REG_MODE_CFG(port), enable);
vsc_write(mac->adapter, REG_PAUSE_CFG(port), v);
vsc_write(mac->adapter, REG_HIGH_LOW_WM(1,port), WM_ENABLE);
vsc_write(mac->adapter, REG_MODE_CFG(port), val);
vsc_write(mac->adapter, REG_MODE_CFG(port), val);
vsc_write(mac->adapter, CRA(4, port, i), 0);
vsc_write(adapter, REG_SW_RESET, 0x80000001);
ret = vsc_write(dev, VSC_SEMAPHORE_OFFSET, counter);
ret = vsc_write(dev, VSC_SEMAPHORE_OFFSET, MLX5_VSC_UNLOCK);
ret = vsc_write(dev, VSC_CTRL_OFFSET, val);
ret = vsc_write(dev, VSC_DATA_OFFSET, data);
ret = vsc_write(dev, VSC_ADDR_OFFSET, address);
ret = vsc_write(dev, VSC_ADDR_OFFSET, address);