vcpu_set_msr
vcpu_set_msr(vcpu, MSR_IA32_SMBASE, smram_gpa);
vcpu_set_msr(vcpu, MSR_KVM_STEAL_TIME, (ulong)st_gva[i] | KVM_MSR_ENABLED);
vcpu_set_msr(vcpu, msr, supported_mask);
vcpu_set_msr(vcpu, MSR_K7_HWCR, 0);
vcpu_set_msr(vcpu, HV_X64_MSR_VP_INDEX, vcpu->id);
vcpu_set_msr(vcpu[1], HV_X64_MSR_VP_INDEX, RECEIVER_VCPU_ID_1);
vcpu_set_msr(vcpu[2], HV_X64_MSR_VP_INDEX, RECEIVER_VCPU_ID_2);
vcpu_set_msr(vcpu, HV_X64_MSR_VP_INDEX, vcpu->id);
vcpu_set_msr(vcpu[1], HV_X64_MSR_VP_INDEX, WORKER_VCPU_ID_1);
vcpu_set_msr(vcpu[2], HV_X64_MSR_VP_INDEX, WORKER_VCPU_ID_2);
vcpu_set_msr(vcpu, msr, reset_val);
vcpu_set_msr(vcpu, MSR_EFER, old_efer | EFER_SVME);
vcpu_set_msr(vcpu, MSR_EFER, old_efer & ~EFER_SVME);
vcpu_set_msr(vcpu, MSR_PLATFORM_INFO,
vcpu_set_msr(*vcpu, MSR_IA32_PERF_CAPABILITIES, perf_capabilities);
vcpu_set_msr(vcpus[i], MSR_IA32_APICBASE, LAPIC_X2APIC);
vcpu_set_msr(vcpuN, MSR_IA32_APICBASE, LAPIC_X2APIC);
vcpu_set_msr(vcpuN, MSR_IA32_APICBASE, LAPIC_DISABLED);
vcpu_set_msr(vcpu, MSR_IA32_TSC, HOST_ADJUST + val);
vcpu_set_msr(vcpu, MSR_IA32_TSC_ADJUST, UNITY * 123456);
vcpu_set_msr(vcpu, MSR_IA32_TSC_ADJUST, val);
vcpu_set_msr(vcpu, MSR_IA32_TSC, TEST_TSC_OFFSET);
vcpu_set_msr(vcpu, msr_index, val & ~BIT_ULL(bit));
vcpu_set_msr(vcpu, msr_index, val);
vcpu_set_msr(vcpu, msr_index, val | BIT_ULL(bit));
vcpu_set_msr(vcpu, msr_index, val);
vcpu_set_msr(vcpu, MSR_IA32_VMX_VMCS_ENUM, 0);
vcpu_set_msr(vcpu, MSR_IA32_VMX_VMCS_ENUM, -1ull);
vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, val | msr_bit | FEAT_CTL_LOCKED);
vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, (val & ~msr_bit) | FEAT_CTL_LOCKED);
vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, val | msr_bit | FEAT_CTL_LOCKED);
vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, (val & ~msr_bit) | FEAT_CTL_LOCKED);
vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, val);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, 0);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, BIT_ULL(bit));
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES,
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
vcpu_set_msr(vcpu, MSR_LBR_TOS, 7);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, 0);
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base);
vcpu_set_msr(vcpu, MSR_IA32_APICBASE, MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
vcpu_set_msr(vcpu, MSR_IA32_XSS, xss_val);