vop2_readl
val = vop2_readl(vop2, dump->base + dump->en_reg);
vop2_readl(vop2, dump->base + (4 * i)),
vop2_readl(vop2, dump->base + (4 * (i + 1))),
vop2_readl(vop2, dump->base + (4 * (i + 2))),
vop2_readl(vop2, dump->base + (4 * (i + 3))));
irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL);
version = vop2_readl(vop2, RK3568_VERSION_INFO);
vop2->old_layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
vop2->old_port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
die = vop2_readl(vop2, RK3568_DSP_IF_EN);
dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
ctrl = vop2_readl(vop2, reg);
die = vop2_readl(vop2, RK3568_DSP_IF_EN);
dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
div = vop2_readl(vop2, RK3568_DSP_IF_CTRL);
return vop2_readl(vop2, RK3568_OVL_PORT_SEL);
return vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
atv_layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
cfg_done = vop2_readl(vop2, RK3568_REG_CFG_DONE);
ovl_ctrl = vop2_readl(vop2, RK3576_OVL_CTRL(vp->id));