drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1005

vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1006

vop2_data = vop2->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1034

drm_dbg_kms(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1041

drm_dbg_kms(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1053

drm_dbg_kms(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1062

drm_dbg_kms(vop2->drm,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1067

if (vop2->version == VOP_VERSION_RK3568 && drm_is_afbc(fb->modifier) && src_w % 4) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1068

drm_dbg_kms(vop2->drm,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1078

drm_dbg_kms(vop2->drm,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1091

struct vop2 *vop2 = win->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1093

drm_dbg(vop2->drm, "%s disable\n", win->data->name);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1162

struct vop2 *vop2 = win->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1243

if (vop2->version == VOP_VERSION_RK3568 && drm_is_afbc(fb->modifier))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1253

drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1259

if (vop2->version > VOP_VERSION_RK3568) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1265

if (vop2->version >= VOP_VERSION_RK3576)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1319

if (vop2->version == VOP_VERSION_RK3568)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1329

if (vop2->version >= VOP_VERSION_RK3576) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1375

vop2_setup_scale(vop2, win, src_w, src_h, dsp_w, dsp_h, fb->format->format);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

140

static void vop2_lock(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

142

mutex_lock(&vop2->vop2_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

145

static void vop2_unlock(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1450

static void vop2_crtc_write_gamma_lut(struct vop2 *vop2, struct drm_crtc *crtc)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1453

const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1463

writel(word, vop2->lut_regs + i * 4);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1467

static void vop2_crtc_atomic_set_gamma_seamless(struct vop2 *vop2,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

147

mutex_unlock(&vop2->vop2_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1471

vop2_writel(vop2, RK3568_LUT_PORT_SEL,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1474

vop2_crtc_write_gamma_lut(vop2, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1478

static void vop2_crtc_atomic_set_gamma_rk356x(struct vop2 *vop2,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1487

vop2_writel(vop2, RK3568_LUT_PORT_SEL, vp->id);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1488

vop2_crtc_write_gamma_lut(vop2, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1492

static void vop2_crtc_atomic_try_set_gamma(struct vop2 *vop2,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1497

if (!vop2->lut_regs)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1505

if (vop2_supports_seamless_gamma_lut_update(vop2))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1506

vop2_crtc_atomic_set_gamma_seamless(vop2, vp, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1508

vop2_crtc_atomic_set_gamma_rk356x(vop2, vp, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1511

static inline void vop2_crtc_atomic_try_set_gamma_locked(struct vop2 *vop2,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1516

vop2_lock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1517

vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1518

vop2_unlock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1553

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1567

vop2->ops->setup_bg_dly(vp);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1612

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1613

const struct vop2_data *vop2_data = vop2->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1636

drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1640

vop2_lock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1644

drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1646

vop2_unlock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1650

if (!vop2->enable_count)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1651

vop2_enable(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1653

vop2->enable_count++;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1675

clock = vop2->ops->setup_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1679

vop2_unlock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1693

if (vop2_output_rg_swap(vop2, vcstate->bus_format))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1728

vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1744

if (vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1752

if (!vop2->pll_hdmiphy0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1758

ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1760

drm_warn(vop2->drm,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1767

if (!vop2->pll_hdmiphy1)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1773

ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1775

drm_warn(vop2->drm,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1792

vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1796

vop2_unlock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1804

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1807

if (!vp->vop2->lut_regs || !crtc_state->color_mgmt_changed ||

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1813

drm_dbg(vop2->drm, "Invalid LUT size; got %d, expected %d\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1818

if (!vop2_supports_seamless_gamma_lut_update(vop2) && vop2_gamma_lut_in_use(vop2, vp)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1819

drm_info(vop2->drm, "Gamma LUT can be enabled for only one CRTC at a time\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1852

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1854

vop2->ops->setup_overlay(vp);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1862

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

1866

vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2019

static void vop2_regs_print(struct vop2 *vop2, struct seq_file *s,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2027

val = vop2_readl(vop2, dump->base + dump->en_reg);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2034

start = vop2->res->start + dump->base;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2037

vop2_readl(vop2, dump->base + (4 * i)),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2038

vop2_readl(vop2, dump->base + (4 * (i + 1))),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2039

vop2_readl(vop2, dump->base + (4 * (i + 2))),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2040

vop2_readl(vop2, dump->base + (4 * (i + 3))));

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2047

struct vop2 *vop2 = node->info_ent->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2055

regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2057

if (vop2->enable_count) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2058

for (i = 0; i < vop2->data->regs_dump_size; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2059

dump = &vop2->data->regs_dump[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2060

vop2_regs_print(vop2, s, dump, active_only);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2088

static void vop2_debugfs_init(struct vop2 *vop2, struct drm_minor *minor)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2096

vop2_debugfs_list[i].data = vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2107

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2110

vop2_debugfs_init(vop2, crtc->dev->primary);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2169

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2174

if (!pm_runtime_get_if_in_use(vop2->dev))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2177

irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2178

vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2189

u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2203

drm_err_ratelimited(vop2->drm, "POST_BUF_EMPTY irq err at vp%d\n", vp->id);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2207

pm_runtime_put(vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2214

struct vop2 *vop2 = data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2215

const struct vop2_data *vop2_data = vop2->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2224

if (!pm_runtime_get_if_in_use(vop2->dev))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2227

if (vop2->version < VOP_VERSION_RK3576) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2229

struct vop2_video_port *vp = &vop2->vps[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2233

irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2234

vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2245

u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2259

drm_err_ratelimited(vop2->drm,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2267

axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2268

vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2269

axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2270

vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2274

drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2279

pm_runtime_put(vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2284

static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2293

ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2299

drm_err(vop2->drm, "failed to initialize plane %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2312

vop2->registered_num_wins - 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2326

struct vop2 *vop2 = win->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2328

if (vop2->data->soc_id == 3566) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2342

static int vop2_create_crtcs(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2344

const struct vop2_data *vop2_data = vop2->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2345

struct drm_device *drm = vop2->drm;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2346

struct device *dev = vop2->dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2361

vp = &vop2->vps[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2362

vp->vop2 = vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2367

vp->dclk = devm_clk_get(vop2->dev, dclk_name);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2374

drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2390

vp = &vop2->vps[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2395

for (j = 0; j < vop2->registered_num_wins; j++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2396

win = &vop2->win[j];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2412

ret = vop2_plane_init(vop2, win, possible_crtcs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2428

for (i = 0; i < vop2->registered_num_wins; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2429

win = &vop2->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2443

vp = &vop2->vps[j];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2453

ret = vop2_plane_init(vop2, win, possible_crtcs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2460

vp = &vop2->vps[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2475

if (vop2->lut_regs) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2489

for (i = 0; i < vop2->data->nr_vps; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2490

struct vop2_video_port *vp = &vop2->vps[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2499

static void vop2_destroy_crtcs(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2501

struct drm_device *drm = vop2->drm;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2520

static int vop2_find_rgb_encoder(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2522

struct device_node *node = vop2->dev->of_node;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2526

for (i = 0; i < vop2->data->nr_vps; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2542

struct vop2 *vop2 = win->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2553

win->reg[i] = devm_regmap_field_alloc(vop2->dev, vop2->map, field);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2561

static int vop2_win_init(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2563

const struct vop2_data *vop2_data = vop2->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2570

win = &vop2->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2575

win->vop2 = vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2577

ret = vop2_regmap_init(win, vop2->data->cluster_reg,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2578

vop2->data->nr_cluster_regs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2580

ret = vop2_regmap_init(win, vop2->data->smart_reg,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2581

vop2->data->nr_smart_regs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2586

vop2->registered_num_wins = vop2_data->win_size;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2622

struct vop2 *vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2632

alloc_size = struct_size(vop2, win, vop2_data->win_size);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2633

vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2634

if (!vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2637

vop2->dev = dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2638

vop2->data = vop2_data;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2639

vop2->ops = vop2_data->ops;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2640

vop2->version = vop2_data->version;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2641

vop2->drm = drm;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2643

dev_set_drvdata(dev, vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2650

vop2->res = res;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2651

vop2->regs = devm_ioremap_resource(dev, res);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2652

if (IS_ERR(vop2->regs))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2653

return PTR_ERR(vop2->regs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2654

vop2->len = resource_size(res);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2656

vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2657

if (IS_ERR(vop2->map))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2658

return PTR_ERR(vop2->map);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2666

ret = vop2_win_init(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2672

vop2->lut_regs = devm_ioremap_resource(dev, res);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2673

if (IS_ERR(vop2->lut_regs))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2674

return PTR_ERR(vop2->lut_regs);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2677

vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2678

if (IS_ERR(vop2->sys_grf))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2679

return dev_err_probe(drm->dev, PTR_ERR(vop2->sys_grf),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2684

vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2685

if (IS_ERR(vop2->vop_grf))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2686

return dev_err_probe(drm->dev, PTR_ERR(vop2->vop_grf),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2691

vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2692

if (IS_ERR(vop2->vo1_grf))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2693

return dev_err_probe(drm->dev, PTR_ERR(vop2->vo1_grf),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2698

vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2699

if (IS_ERR(vop2->sys_pmu))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2700

return dev_err_probe(drm->dev, PTR_ERR(vop2->sys_pmu),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2704

vop2->hclk = devm_clk_get(vop2->dev, "hclk");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2705

if (IS_ERR(vop2->hclk))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2706

return dev_err_probe(drm->dev, PTR_ERR(vop2->hclk),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2709

vop2->aclk = devm_clk_get(vop2->dev, "aclk");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2710

if (IS_ERR(vop2->aclk))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2711

return dev_err_probe(drm->dev, PTR_ERR(vop2->aclk),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2714

vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2715

if (IS_ERR(vop2->pclk))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2716

return dev_err_probe(drm->dev, PTR_ERR(vop2->pclk),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2719

vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2720

if (IS_ERR(vop2->pll_hdmiphy0))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2721

return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy0),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2724

vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2725

if (IS_ERR(vop2->pll_hdmiphy1))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2726

return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy1),

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2729

vop2->irq = platform_get_irq(pdev, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2730

if (vop2->irq < 0)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2731

return dev_err_probe(drm->dev, vop2->irq, "cannot find irq for vop2\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2733

mutex_init(&vop2->vop2_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2734

mutex_init(&vop2->ovl_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2736

ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2740

ret = vop2_create_crtcs(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2744

if (vop2->version >= VOP_VERSION_RK3576) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2768

ret = vop2_find_rgb_encoder(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2770

vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2771

vop2->drm, ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2772

if (IS_ERR(vop2->rgb)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2773

if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2774

ret = PTR_ERR(vop2->rgb);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2777

vop2->rgb = NULL;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2781

rockchip_drm_dma_init_device(vop2->drm, vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2788

vop2_destroy_crtcs(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2795

struct vop2 *vop2 = dev_get_drvdata(dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2799

if (vop2->rgb)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2800

rockchip_rgb_fini(vop2->rgb);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

2802

vop2_destroy_crtcs(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

338

static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

340

if (vop2->version == VOP_VERSION_RK3588) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

374

struct vop2 *vop2 = win->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

382

if (vop2->version == VOP_VERSION_RK3568 && vop2_cluster_window(win) &&

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

384

drm_dbg_kms(vop2->drm,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

390

if (vop2->version == VOP_VERSION_RK3588 && !drm_is_afbc(modifier) &&

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

392

drm_dbg_kms(vop2->drm, "Only support 10bpc format with afbc\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

549

static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

591

drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

733

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

735

vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

736

vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

741

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

743

vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

746

static int vop2_core_clks_prepare_enable(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

750

ret = clk_prepare_enable(vop2->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

752

drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

756

ret = clk_prepare_enable(vop2->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

758

drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

762

ret = clk_prepare_enable(vop2->pclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

764

drm_err(vop2->drm, "failed to enable pclk - %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

770

clk_disable_unprepare(vop2->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

772

clk_disable_unprepare(vop2->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

777

static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

781

pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

785

vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

788

static void vop2_enable(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

793

ret = pm_runtime_resume_and_get(vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

795

drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

799

ret = vop2_core_clks_prepare_enable(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

801

pm_runtime_put_sync(vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

805

ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

807

drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

811

version = vop2_readl(vop2, RK3568_VERSION_INFO);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

812

if (version != vop2->version) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

813

drm_err(vop2->drm, "Hardware version(0x%08x) mismatch\n", version);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

821

if (vop2->data->soc_id == 3566)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

822

vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

824

if (vop2->version == VOP_VERSION_RK3588)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

825

rk3588_vop2_power_domain_enable_all(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

827

if (vop2->version <= VOP_VERSION_RK3588) {

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

828

vop2->old_layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

829

vop2->old_port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

832

vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

838

regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

841

vop2_writel(vop2, RK3568_SYS0_INT_CLR,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

843

vop2_writel(vop2, RK3568_SYS0_INT_EN,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

845

vop2_writel(vop2, RK3568_SYS1_INT_CLR,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

847

vop2_writel(vop2, RK3568_SYS1_INT_EN,

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

851

static void vop2_disable(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

853

rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

855

pm_runtime_put_sync(vop2->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

857

regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

859

clk_disable_unprepare(vop2->pclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

860

clk_disable_unprepare(vop2->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

861

clk_disable_unprepare(vop2->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

885

drm_err(vp->vop2->drm, "display LUT RAM enable timeout!\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

908

static inline bool vop2_supports_seamless_gamma_lut_update(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

910

return vop2->version != VOP_VERSION_RK3568;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

913

static bool vop2_gamma_lut_in_use(struct vop2 *vop2, struct vop2_video_port *vp)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

915

const int nr_vps = vop2->data->nr_vps;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

919

if (vop2_vp_dsp_lut_is_enabled(&vop2->vps[gamma_en_vp_id]))

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

929

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

933

vop2_lock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

956

drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

965

vop2->enable_count--;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

967

if (!vop2->enable_count)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

968

vop2_disable(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

970

vop2_unlock(vop2);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

990

struct vop2 *vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

206

struct vop2 *vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

238

struct vop2 *vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

799

static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

801

regmap_write(vop2->map, offset, v);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

806

regmap_write(vp->vop2->map, vp->data->offset + offset, v);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

809

static inline u32 vop2_readl(struct vop2 *vop2, u32 offset)

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

813

regmap_read(vop2->map, offset, &val);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

822

regmap_read(vp->vop2->map, vp->data->offset + offset, &val);

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

858

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

863

regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1377

static struct vop2_win *vop2_find_win_by_phys_id(struct vop2 *vop2, uint8_t phys_id)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1382

for (i = 0; i < vop2->data->win_size; i++) {

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1383

win = &vop2->win[i];

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1393

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1397

die = vop2_readl(vop2, RK3568_DSP_IF_EN);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1398

dip = vop2_readl(vop2, RK3568_DSP_IF_POL);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1408

regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1410

regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1455

drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1461

vop2_writel(vop2, RK3568_DSP_IF_EN, die);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1462

vop2_writel(vop2, RK3568_DSP_IF_POL, dip);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1469

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1522

drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1526

ctrl = vop2_readl(vop2, reg);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1535

vop2_writel(vop2, reg, ctrl);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1571

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1621

drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld Hz\n",

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1638

drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld Hz\n",

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1657

drm_dbg(vop2->drm, "dclk: %ld, pixclk_div: %d, dclk_div: %d\n",

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1691

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1704

die = vop2_readl(vop2, RK3568_DSP_IF_EN);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1705

dip = vop2_readl(vop2, RK3568_DSP_IF_POL);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1706

div = vop2_readl(vop2, RK3568_DSP_IF_CTRL);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1718

regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(1), 1));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1719

regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0,

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1731

regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(4), 1));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1732

regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0,

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1743

regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(0), 1));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1753

regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(3), 1));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1786

drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1793

vop2_writel(vop2, RK3568_DSP_IF_EN, die);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1794

vop2_writel(vop2, RK3568_DSP_IF_CTRL, div);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1795

vop2_writel(vop2, RK3568_DSP_IF_POL, dip);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1866

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1868

u32 layer_sel = vop2->old_layer_sel;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1878

win = vop2_find_win_by_phys_id(vop2, phys_id);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1894

static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1939

if (vop2->version <= VOP_VERSION_RK3588) {

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1951

vop2_writel(vop2, src_color_ctrl_reg + offset, alpha.src_color_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1952

vop2_writel(vop2, dst_color_ctrl_reg + offset, alpha.dst_color_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1953

vop2_writel(vop2, src_alpha_ctrl_reg + offset, alpha.src_alpha_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1954

vop2_writel(vop2, dst_alpha_ctrl_reg + offset, alpha.dst_alpha_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1959

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1972

if (vop2->version <= VOP_VERSION_RK3588)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

1995

if (vop2->version <= VOP_VERSION_RK3588) {

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2054

vop2_writel(vop2, src_color_ctrl_reg + offset, alpha.src_color_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2055

vop2_writel(vop2, dst_color_ctrl_reg + offset, alpha.dst_color_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2056

vop2_writel(vop2, src_alpha_ctrl_reg + offset, alpha.src_alpha_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2057

vop2_writel(vop2, dst_alpha_ctrl_reg + offset, alpha.dst_alpha_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2061

if (vop2->version <= VOP_VERSION_RK3588) {

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2083

vop2_writel(vop2, src_color_ctrl_reg, alpha.src_color_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2084

vop2_writel(vop2, dst_color_ctrl_reg, alpha.dst_color_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2085

vop2_writel(vop2, src_alpha_ctrl_reg, alpha.src_alpha_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2086

vop2_writel(vop2, dst_alpha_ctrl_reg, alpha.dst_alpha_ctrl.val);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2088

vop2_writel(vop2, src_color_ctrl_reg, 0);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2093

static u32 rk3568_vop2_read_port_mux(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2095

return vop2_readl(vop2, RK3568_OVL_PORT_SEL);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2098

static void rk3568_vop2_wait_for_port_mux_done(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2106

ret = readx_poll_timeout_atomic(rk3568_vop2_read_port_mux, vop2, port_mux_sel,

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2107

port_mux_sel == vop2->old_port_sel, 10, 50 * 1000);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2109

DRM_DEV_ERROR(vop2->dev, "wait port_mux done timeout: 0x%x--0x%x\n",

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2110

port_mux_sel, vop2->old_port_sel);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2113

static u32 rk3568_vop2_read_layer_cfg(struct vop2 *vop2)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2115

return vop2_readl(vop2, RK3568_OVL_LAYER_SEL);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2118

static void rk3568_vop2_wait_for_layer_cfg_done(struct vop2 *vop2, u32 cfg)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2126

ret = readx_poll_timeout_atomic(rk3568_vop2_read_layer_cfg, vop2, atv_layer_cfg,

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2129

DRM_DEV_ERROR(vop2->dev, "wait layer cfg done timeout: 0x%x--0x%x\n",

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2135

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2149

struct vop2_video_port *vp0 = &vop2->vps[0];

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2150

struct vop2_video_port *vp1 = &vop2->vps[1];

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2151

struct vop2_video_port *vp2 = &vop2->vps[2];

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2154

mutex_lock(&vop2->ovl_lock);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2155

ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2164

old_port_sel = vop2->old_port_sel;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2187

if (vop2->version == VOP_VERSION_RK3588)

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2190

atv_layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2191

old_layer_sel = vop2->old_layer_sel;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2196

ofs += vop2->vps[i].nlayers;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2206

for (old_layer_id = 0; old_layer_id < vop2->data->win_size; old_layer_id++) {

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2215

for (i = 0; i < vop2->data->win_size; i++) {

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2216

old_win = &vop2->win[i];

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2276

vop2->old_layer_sel = layer_sel;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2277

vop2->old_port_sel = port_sel;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2294

vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2297

vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2299

rk3568_vop2_wait_for_port_mux_done(vop2);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2303

cfg_done = vop2_readl(vop2, RK3568_REG_CFG_DONE);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2304

cfg_done &= (BIT(vop2->data->nr_vps) - 1);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2310

rk3568_vop2_wait_for_layer_cfg_done(vop2, vop2->old_layer_sel);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2313

vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2314

mutex_unlock(&vop2->ovl_lock);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2319

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2324

for (i = 0; i < vop2->data->win_size; i++) {

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2327

win = &vop2->win[i];

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2356

vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2357

vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2362

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2376

vop2_setup_cluster_alpha(vop2, win);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2390

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2395

ovl_ctrl = vop2_readl(vop2, RK3576_OVL_CTRL(vp->id));

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2401

vop2_writel(vop2, RK3576_OVL_CTRL(vp->id), ovl_ctrl);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2412

vop2_writel(vop2, RK3576_OVL_LAYER_SEL(vp->id), layer_sel);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2428

struct vop2 *vop2 = vp->vop2;

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2441

vop2_setup_cluster_alpha(vop2, win);

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2462

vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

2482

vop2_writel(vp->vop2, RK3576_OVL_BG_MIX_CTRL(vp->id),