drivers/gpu/drm/rockchip/rockchip_drm_vop.c

100

#define VOP_AFBC_SET(vop, name, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1001

VOP_WIN_SET(vop, win, x_mir_en,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1017

VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1018

VOP_WIN_SET(vop, win, uv_mst, dma_addr);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

102

if ((vop)->data->afbc) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1021

VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1028

VOP_WIN_SET(vop, win, uv_swap, uv_swap);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

103

vop_reg_set((vop), &(vop)->data->afbc->name, \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1032

scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1036

VOP_WIN_SET(vop, win, act_info, act_info);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1037

VOP_WIN_SET(vop, win, dsp_info, dsp_info);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1038

VOP_WIN_SET(vop, win, dsp_st, dsp_st);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1040

rb_swap = has_rb_swapped(vop->data->version, fb->format->format);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1041

VOP_WIN_SET(vop, win, rb_swap, rb_swap);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1051

VOP_WIN_SET(vop, win, dst_alpha_ctl,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1058

VOP_WIN_SET(vop, win, src_alpha_ctl, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1060

VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1061

VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1062

VOP_WIN_SET(vop, win, alpha_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1064

VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1065

VOP_WIN_SET(vop, win, alpha_en, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1068

VOP_WIN_SET(vop, win, enable, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1069

vop->win_enabled |= BIT(win_index);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

107

#define to_vop(x) container_of(x, struct vop, crtc)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1070

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1112

struct vop *vop = to_vop(plane->state->crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1125

if (vop->is_enabled) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1127

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1128

vop_cfg_done(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1129

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1142

drm_flip_work_queue(&vop->fb_unref_work, old_fb);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1143

set_bit(VOP_PENDING_FB_UNREF, &vop->pending);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1168

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1171

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1174

spin_lock_irqsave(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1176

VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1177

VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1179

spin_unlock_irqrestore(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1186

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1189

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1192

spin_lock_irqsave(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1194

VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1196

spin_unlock_irqrestore(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1202

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1204

if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1214

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1243

rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1245

rate = clk_round_rate(vop->dclk,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1252

static bool vop_dsp_lut_is_enabled(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1254

return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1257

static u32 vop_lut_buffer_index(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1259

return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1262

static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1265

unsigned int i, bpc = ilog2(vop->data->lut_size);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1273

writel(word, vop->lut_regs + i * 4);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1277

static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1285

if (!vop->lut_regs)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1288

if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1293

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1294

VOP_REG_SET(vop, common, dsp_lut_en, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1295

vop_cfg_done(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1296

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1302

ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1305

DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1316

old_idx = vop_lut_buffer_index(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1319

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1320

vop_crtc_write_gamma_lut(vop, crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1321

VOP_REG_SET(vop, common, dsp_lut_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1322

VOP_REG_SET(vop, common, update_gamma_lut, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1323

vop_cfg_done(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1324

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1326

if (VOP_HAS_REG(vop, common, update_gamma_lut)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1327

ret = readx_poll_timeout(vop_lut_buffer_index, vop,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1330

DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1338

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1339

VOP_REG_SET(vop, common, update_gamma_lut, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1340

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1351

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1359

vop_crtc_gamma_set(vop, crtc, old_crtc_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

136

struct vop *vop;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1367

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1368

const struct vop_data *vop_data = vop->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1391

mutex_lock(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1393

WARN_ON(vop->event);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1397

mutex_unlock(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1398

DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1405

VOP_REG_SET(vop, output, pin_pol, pin_pol);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1406

VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1410

VOP_REG_SET(vop, output, rgb_dclk_pol, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1411

VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1412

VOP_REG_SET(vop, output, rgb_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1415

VOP_REG_SET(vop, output, edp_dclk_pol, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1416

VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1417

VOP_REG_SET(vop, output, edp_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1420

VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1421

VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1422

VOP_REG_SET(vop, output, hdmi_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1425

VOP_REG_SET(vop, output, mipi_dclk_pol, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1426

VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1427

VOP_REG_SET(vop, output, mipi_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1428

VOP_REG_SET(vop, output, mipi_dual_channel_en,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1432

VOP_REG_SET(vop, output, dp_dclk_pol, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1433

VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1434

VOP_REG_SET(vop, output, dp_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1437

DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1449

VOP_REG_SET(vop, common, pre_dither_down, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1451

VOP_REG_SET(vop, common, pre_dither_down, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1454

VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1455

VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1456

VOP_REG_SET(vop, common, dither_down_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1458

VOP_REG_SET(vop, common, dither_down_en, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1461

VOP_REG_SET(vop, common, out_mode, s->output_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1463

VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1466

VOP_REG_SET(vop, modeset, hact_st_end, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1467

VOP_REG_SET(vop, modeset, hpost_st_end, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1469

VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1472

VOP_REG_SET(vop, modeset, vact_st_end, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1473

VOP_REG_SET(vop, modeset, vpost_st_end, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1475

VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1477

clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1479

VOP_REG_SET(vop, common, standby, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1480

mutex_unlock(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1488

vop_crtc_gamma_set(vop, crtc, old_state);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1491

static bool vop_fs_irq_is_pending(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1493

return VOP_INTR_GET_TYPE(vop, status, FS_INTR);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1496

static void vop_wait_for_irq_handler(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1509

ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1512

DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1514

synchronize_irq(vop->irq);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1522

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1528

if (vop->lut_regs && crtc_state->color_mgmt_changed &&

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1571

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1576

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1579

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1583

VOP_AFBC_SET(vop, enable, s->enable_afbc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1584

vop_cfg_done(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1587

if (VOP_HAS_REG(vop, common, dma_stop))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1588

VOP_REG_SET(vop, common, dma_stop, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1590

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1597

vop_wait_for_irq_handler(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1602

WARN_ON(vop->event);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1604

vop->event = crtc->state->event;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1619

drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1620

set_bit(VOP_PENDING_FB_UNREF, &vop->pending);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1673

static struct drm_connector *vop_get_edp_connector(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1678

drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1693

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1697

connector = vop_get_edp_connector(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1752

struct vop *vop = container_of(work, struct vop, fb_unref_work);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1755

drm_crtc_vblank_put(&vop->crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1759

static void vop_handle_vblank(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1761

struct drm_device *drm = vop->drm_dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1762

struct drm_crtc *crtc = &vop->crtc;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1765

if (vop->event) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1766

drm_crtc_send_vblank_event(crtc, vop->event);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1768

vop->event = NULL;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1772

if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1773

drm_flip_work_commit(&vop->fb_unref_work, system_dfl_wq);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1778

struct vop *vop = data;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1779

struct drm_crtc *crtc = &vop->crtc;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1787

if (!pm_runtime_get_if_in_use(vop->dev))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1790

if (vop_core_clks_enable(vop)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1791

DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1799

spin_lock(&vop->irq_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1801

active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1804

VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1806

spin_unlock(&vop->irq_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1813

complete(&vop->dsp_hold_completion);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1819

complete(&vop->line_flag_completion);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1826

vop_handle_vblank(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1833

DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1837

vop_core_clks_disable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1839

pm_runtime_put(vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1855

static int vop_create_crtc(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1857

const struct vop_data *vop_data = vop->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1858

struct device *dev = vop->dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1859

struct drm_device *drm_dev = vop->drm_dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1861

struct drm_crtc *crtc = &vop->crtc;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1872

struct vop_win *vop_win = &vop->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1879

ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1886

DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1906

if (vop->lut_regs) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

191

static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1916

struct vop_win *vop_win = &vop->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1923

ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

193

return readl(vop->regs + offset);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1931

DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1941

DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1947

drm_flip_work_init(&vop->fb_unref_work, "fb_unref",

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1950

init_completion(&vop->dsp_hold_completion);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1951

init_completion(&vop->line_flag_completion);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1956

DRM_DEV_DEBUG_KMS(vop->dev,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

196

static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1971

static void vop_destroy_crtc(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1973

struct drm_crtc *crtc = &vop->crtc;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1974

struct drm_device *drm_dev = vop->drm_dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

199

return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

1998

drm_flip_work_cleanup(&vop->fb_unref_work);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2001

static int vop_initial(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2006

vop->hclk = devm_clk_get(vop->dev, "hclk_vop");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2007

if (IS_ERR(vop->hclk)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2008

DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2009

return PTR_ERR(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2011

vop->aclk = devm_clk_get(vop->dev, "aclk_vop");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2012

if (IS_ERR(vop->aclk)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2013

DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2014

return PTR_ERR(vop->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2016

vop->dclk = devm_clk_get(vop->dev, "dclk_vop");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2017

if (IS_ERR(vop->dclk)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2018

DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2019

return PTR_ERR(vop->dclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

202

static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2022

ret = pm_runtime_resume_and_get(vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2024

DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2028

ret = clk_prepare(vop->dclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2030

DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2035

ret = clk_prepare_enable(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2037

DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2041

ret = clk_prepare_enable(vop->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2043

DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2050

ahb_rst = devm_reset_control_get(vop->dev, "ahb");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2052

DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2060

VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2061

VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2063

for (i = 0; i < vop->len; i += sizeof(u32))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2064

vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2066

VOP_REG_SET(vop, misc, global_regdone_en, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2067

VOP_REG_SET(vop, common, dsp_blank, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2069

for (i = 0; i < vop->data->win_size; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2070

struct vop_win *vop_win = &vop->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2074

VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2075

vop_win_disable(vop, vop_win);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2076

VOP_WIN_SET(vop, win, gate, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2079

vop_cfg_done(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2084

vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2085

if (IS_ERR(vop->dclk_rst)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2086

DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2087

ret = PTR_ERR(vop->dclk_rst);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

209

DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2090

reset_control_assert(vop->dclk_rst);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2092

reset_control_deassert(vop->dclk_rst);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2094

clk_disable(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2095

clk_disable(vop->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2097

vop->is_enabled = false;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2099

pm_runtime_put_sync(vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2104

clk_disable_unprepare(vop->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2106

clk_disable_unprepare(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2108

clk_unprepare(vop->dclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2110

pm_runtime_put_sync(vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2117

static void vop_win_init(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2119

const struct vop_data *vop_data = vop->data;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2123

struct vop_win *vop_win = &vop->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2127

vop_win->vop = vop;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2146

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2150

if (!crtc || !vop->is_enabled)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2153

mutex_lock(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2159

if (vop_line_flag_irq_is_enabled(vop)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2164

reinit_completion(&vop->line_flag_completion);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2165

vop_line_flag_irq_enable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2167

jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2169

vop_line_flag_irq_disable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2172

DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2178

mutex_unlock(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2188

struct vop *vop;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2197

vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2199

if (!vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

220

uint32_t cached_val = vop->regsbak[offset >> 2];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2202

vop->dev = dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2203

vop->data = vop_data;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2204

vop->drm_dev = drm_dev;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2205

dev_set_drvdata(dev, vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2207

vop_win_init(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2210

vop->regs = devm_ioremap_resource(dev, res);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2211

if (IS_ERR(vop->regs))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2212

return PTR_ERR(vop->regs);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2213

vop->len = resource_size(res);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2221

vop->lut_regs = devm_ioremap_resource(dev, res);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2222

if (IS_ERR(vop->lut_regs))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2223

return PTR_ERR(vop->lut_regs);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2226

vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2227

if (!vop->regsbak)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

223

vop->regsbak[offset >> 2] = v;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2235

vop->irq = (unsigned int)irq;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2237

spin_lock_init(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2238

spin_lock_init(&vop->irq_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2239

mutex_init(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2241

ret = vop_create_crtc(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2247

ret = vop_initial(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2254

ret = devm_request_irq(dev, vop->irq, vop_isr,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2255

IRQF_SHARED, dev_name(dev), vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2259

if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2260

vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2261

if (IS_ERR(vop->rgb)) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2262

ret = PTR_ERR(vop->rgb);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

227

writel_relaxed(v, vop->regs + offset);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2273

vop_destroy_crtc(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2279

struct vop *vop = dev_get_drvdata(dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2281

if (vop->rgb)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2282

rockchip_rgb_fini(vop->rgb);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2285

vop_destroy_crtc(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2287

clk_unprepare(vop->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2288

clk_unprepare(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

2289

clk_unprepare(vop->dclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

229

writel(v, vop->regs + offset);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

232

static inline uint32_t vop_get_intr_type(struct vop *vop,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

236

uint32_t regs = vop_read_reg(vop, 0, reg);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

238

for (i = 0; i < vop->data->intr->nintrs; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

239

if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

240

ret |= vop->data->intr->intrs[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

246

static inline void vop_cfg_done(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

248

VOP_REG_SET(vop, common, cfg_done, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

382

static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

401

DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

406

VOP_SCL_SET(vop, win, scale_yrgb_x,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

408

VOP_SCL_SET(vop, win, scale_yrgb_y,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

411

VOP_SCL_SET(vop, win, scale_cbcr_x,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

413

VOP_SCL_SET(vop, win, scale_cbcr_y,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

436

VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

439

DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

443

DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

45

#define VOP_WIN_SET(vop, win, name, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

455

VOP_SCL_SET(vop, win, scale_yrgb_x, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

458

VOP_SCL_SET(vop, win, scale_yrgb_y, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

46

vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

460

VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

461

VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

463

VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

464

VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

465

VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

466

VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

467

VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

47

#define VOP_SCL_SET(vop, win, name, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

471

VOP_SCL_SET(vop, win, scale_cbcr_x, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

474

VOP_SCL_SET(vop, win, scale_cbcr_y, val);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

476

VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

477

VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

478

VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

479

VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

48

vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

480

VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

481

VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

482

VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

486

static void vop_dsp_hold_valid_irq_enable(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

49

#define VOP_SCL_SET_EXT(vop, win, name, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

490

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

493

spin_lock_irqsave(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

495

VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

496

VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

498

spin_unlock_irqrestore(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

50

vop_reg_set(vop, &win->phy->scl->ext->name, \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

501

static void vop_dsp_hold_valid_irq_disable(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

505

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

508

spin_lock_irqsave(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

510

VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

512

spin_unlock_irqrestore(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

53

#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

537

static bool vop_line_flag_irq_is_enabled(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

542

spin_lock_irqsave(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

544

line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

546

spin_unlock_irqrestore(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

551

static void vop_line_flag_irq_enable(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

555

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

558

spin_lock_irqsave(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

56

vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

560

VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

561

VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

563

spin_unlock_irqrestore(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

566

static void vop_line_flag_irq_disable(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

570

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

573

spin_lock_irqsave(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

575

VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

577

spin_unlock_irqrestore(&vop->irq_lock, flags);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

580

static int vop_core_clks_enable(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

584

ret = clk_enable(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

588

ret = clk_enable(vop->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

59

#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

595

clk_disable(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

599

static void vop_core_clks_disable(struct vop *vop)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

601

clk_disable(vop->aclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

602

clk_disable(vop->hclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

605

static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

610

VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

611

VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

612

VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

613

VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

616

VOP_WIN_SET(vop, win, enable, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

617

vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

62

vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

622

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

625

ret = pm_runtime_resume_and_get(vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

627

DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

631

ret = vop_core_clks_enable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

635

ret = clk_enable(vop->dclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

645

ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

647

DRM_DEV_ERROR(vop->dev,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

65

#define VOP_INTR_SET_MASK(vop, name, mask, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

652

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

653

for (i = 0; i < vop->len; i += 4)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

654

writel_relaxed(vop->regsbak[i / 4], vop->regs + i);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

66

vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

666

for (i = 0; i < vop->data->win_size; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

667

struct vop_win *vop_win = &vop->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

669

vop_win_disable(vop, vop_win);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

673

if (vop->data->afbc) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

678

VOP_AFBC_SET(vop, enable, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

68

#define VOP_REG_SET(vop, group, name, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

683

vop_cfg_done(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

685

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

69

vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

690

vop->is_enabled = true;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

692

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

694

VOP_REG_SET(vop, common, standby, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

696

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

703

clk_disable(vop->dclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

705

vop_core_clks_disable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

707

pm_runtime_put_sync(vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

71

#define VOP_HAS_REG(vop, group, name) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

713

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

716

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

718

for (i = 0; i < vop->data->win_size; i++) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

719

struct vop_win *vop_win = &vop->win[i];

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

72

(!!(vop->data->group->name.mask))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

722

VOP_WIN_SET(vop, win, enable,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

723

enabled && (vop->win_enabled & BIT(i)));

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

725

vop_cfg_done(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

727

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

733

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

735

WARN_ON(vop->event);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

74

#define VOP_INTR_SET_TYPE(vop, name, type, v) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

742

mutex_lock(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

753

reinit_completion(&vop->dsp_hold_completion);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

754

vop_dsp_hold_valid_irq_enable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

756

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

758

VOP_REG_SET(vop, common, standby, 1);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

760

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

762

if (!wait_for_completion_timeout(&vop->dsp_hold_completion,

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

766

vop_dsp_hold_valid_irq_disable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

768

vop->is_enabled = false;

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

77

for (i = 0; i < vop->data->intr->nintrs; i++) { \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

773

rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

775

clk_disable(vop->dclk);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

776

vop_core_clks_disable(vop);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

777

pm_runtime_put(vop->dev);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

779

mutex_unlock(&vop->vop_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

78

if (vop->data->intr->intrs[i] & type) { \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

83

VOP_INTR_SET_MASK(vop, name, mask, reg); \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

85

#define VOP_INTR_GET_TYPE(vop, name, type) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

86

vop_get_intr_type(vop, &vop->data->intr->name, type)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

862

struct vop *vop = to_vop(crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

864

if (!vop->data->afbc) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

88

#define VOP_WIN_GET(vop, win, name) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

89

vop_read_reg(vop, win->base, &win->phy->name)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

897

struct vop *vop = to_vop(old_state->crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

902

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

904

vop_win_disable(vop, vop_win);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

906

spin_unlock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

918

struct vop *vop = to_vop(new_state->crtc);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

94

#define VOP_WIN_GET_YRGBADDR(vop, win) \

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

942

if (WARN_ON(!vop->is_enabled))

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

95

vop_readl(vop, win->base + win->phy->yrgb_mst.offset)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

98

((vop_win) - (vop_win)->vop->win)

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

982

spin_lock(&vop->reg_lock);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

987

VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

988

VOP_AFBC_SET(vop, hreg_block_split, 0);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

989

VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

990

VOP_AFBC_SET(vop, hdr_ptr, dma_addr);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

991

VOP_AFBC_SET(vop, pic_size, act_info);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

994

VOP_WIN_SET(vop, win, format, format);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

995

VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

996

VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

997

VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

998

VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

999

VOP_WIN_SET(vop, win, y_mir_en,

drivers/gpu/drm/rockchip/rockchip_lvds.c

378

int vop;

drivers/gpu/drm/rockchip/rockchip_lvds.c

380

vop = drm_of_encoder_active_endpoint_id(lvds->dev->of_node, encoder);

drivers/gpu/drm/rockchip/rockchip_lvds.c

381

if (vop < 0)

drivers/gpu/drm/rockchip/rockchip_lvds.c

382

return vop;

drivers/gpu/drm/rockchip/rockchip_lvds.c

386

PX30_LVDS_VOP_SEL(vop));

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

143

u8 *vop;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

153

vop = vop_6110_ntsc_cif;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

156

vop = vop_6110_pal_cif;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

161

vop = vop_6010_ntsc_cif;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

164

vop = vop_6010_pal_cif;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

174

vop = vop_6110_ntsc_d1;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

177

vop = vop_6110_pal_d1;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

182

vop = vop_6010_ntsc_d1;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

185

vop = vop_6010_pal_d1;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

191

memcpy(solo_enc->vop, vop, vop_len);

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

198

vop = solo_enc->vop;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

201

vop[22] = fps >> 4;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

202

vop[23] = ((fps << 4) & 0xf0) | 0x0c

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

204

vop[24] = (interval >> 5) & 0xff;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

205

vop[25] = ((interval << 3) & 0xf8) | 0x04;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

211

vop = solo_enc->jpeg_header;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

212

vop[SOF0_START + 5] = 0xff & (solo_enc->height >> 8);

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

213

vop[SOF0_START + 6] = 0xff & solo_enc->height;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

214

vop[SOF0_START + 7] = 0xff & (solo_enc->width >> 8);

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

215

vop[SOF0_START + 8] = 0xff & solo_enc->width;

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

217

memcpy(vop + DQT_START,

drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c

744

solo_enc->vop, solo_enc->vop_len);

drivers/media/pci/solo6x10/solo6x10.h

163

u8 vop[64];

drivers/net/wireless/realtek/rtl8xxxu/core.c

2587

int hip, mgp, bkp, bep, vip, vop;

drivers/net/wireless/realtek/rtl8xxxu/core.c

2616

vop = 0;

drivers/net/wireless/realtek/rtl8xxxu/core.c

2646

vop = 0;

drivers/net/wireless/realtek/rtl8xxxu/core.c

2661

vop = viq ^ 3;

drivers/net/wireless/realtek/rtl8xxxu/core.c

2696

usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);

drivers/soc/mediatek/mtk-svs.c

1008

vop = (shift_byte < REG_BYTES) ? &vop30 :

drivers/soc/mediatek/mtk-svs.c

1010

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);

drivers/soc/mediatek/mtk-svs.c

940

u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;

drivers/soc/mediatek/mtk-svs.c

957

vop = (shift_byte < REG_BYTES) ? &vop30 :

drivers/soc/mediatek/mtk-svs.c

959

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);

drivers/soc/mediatek/mtk-svs.c

969

vop = (shift_byte < REG_BYTES) ? &vop30 :

drivers/soc/mediatek/mtk-svs.c

971

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);

drivers/soc/mediatek/mtk-svs.c

991

vop = (shift_byte < REG_BYTES) ? &vop30 :

drivers/soc/mediatek/mtk-svs.c

993

svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);