arch/x86/kvm/vmx/pmu_intel.c

661

vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

662

vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

664

vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

667

vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/pmu_intel.c

668

vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set);

arch/x86/kvm/vmx/vmx.c

4259

vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4277

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4278

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4279

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4280

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4282

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4283

vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);

arch/x86/kvm/vmx/vmx.c

4315

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i,

arch/x86/kvm/vmx/vmx.c

4317

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4321

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PERFCTR0 + i,

arch/x86/kvm/vmx/vmx.c

4323

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PMC0 + i,

arch/x86/kvm/vmx/vmx.c

4328

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR0 + i,

arch/x86/kvm/vmx/vmx.c

4331

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_FIXED_CTR0 + i,

arch/x86/kvm/vmx/vmx.c

4335

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_STATUS,

arch/x86/kvm/vmx/vmx.c

4337

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL,

arch/x86/kvm/vmx/vmx.c

4339

vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,

arch/x86/kvm/vmx/vmx.c

4377

vmx_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW,

arch/x86/kvm/vmx/vmx.c

4381

vmx_set_intercept_for_msr(vcpu, MSR_IA32_XFD_ERR, MSR_TYPE_R,

arch/x86/kvm/vmx/vmx.c

4385

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W,

arch/x86/kvm/vmx/vmx.c

4389

vmx_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,

arch/x86/kvm/vmx/vmx.c

4395

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL0_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4396

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL1_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4397

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL2_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4398

vmx_set_intercept_for_msr(vcpu, MSR_IA32_PL3_SSP, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4405

vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.c

4406

vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET, MSR_TYPE_RW, intercept);

arch/x86/kvm/vmx/vmx.h

380

void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type, bool set);

arch/x86/kvm/vmx/vmx.h

385

vmx_set_intercept_for_msr(vcpu, msr, type, false);

arch/x86/kvm/vmx/vmx.h

391

vmx_set_intercept_for_msr(vcpu, msr, type, true);