vmcs_readl
*s_cet = vmcs_readl(GUEST_S_CET);
*ssp = vmcs_readl(GUEST_SSP);
*ssp_tbl = vmcs_readl(GUEST_INTR_SSP_TABLE);
/*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
/*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
/*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
/*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
WARN_ON(kvm_set_dr(vcpu, 7, vmcs_readl(GUEST_DR7)));
vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW));
vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
vmx_set_cr4(vcpu, vmcs_readl(CR4_READ_SHADOW));
vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
rflags = vmcs_readl(GUEST_RFLAGS);
msr_info->data = vmcs_readl(GUEST_FS_BASE);
msr_info->data = vmcs_readl(GUEST_GS_BASE);
msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
msr_info->data = vmcs_readl(GUEST_S_CET);
msr_info->data = vmcs_readl(GUEST_SSP);
msr_info->data = vmcs_readl(GUEST_INTR_SSP_TABLE);
vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & guest_owned_bits;
flags = vmcs_readl(GUEST_RFLAGS);
vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
(vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
flags = vmcs_readl(GUEST_RFLAGS);
vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
dt->address = vmcs_readl(GUEST_IDTR_BASE);
dt->address = vmcs_readl(GUEST_GDTR_BASE);
vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS) | DR6_BS);
kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
dr7 = vmcs_readl(GUEST_DR7);
vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
cr4 = vmcs_readl(GUEST_CR4);
vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
vmcs_readl(CR0_GUEST_HOST_MASK));
cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
vmcs_readl(GUEST_SYSENTER_ESP),
vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
vmcs_readl(GUEST_S_CET), vmcs_readl(GUEST_SSP),
vmcs_readl(GUEST_INTR_SSP_TABLE));
vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
vmcs_readl(HOST_TR_BASE));
vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
vmcs_readl(HOST_CR4));
vmcs_readl(HOST_IA32_SYSENTER_ESP),
vmcs_readl(HOST_IA32_SYSENTER_EIP));
vmcs_readl(HOST_S_CET), vmcs_readl(HOST_SSP),
vmcs_readl(HOST_INTR_SSP_TABLE));
vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
*p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
vt->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);