vlv_punit_read
val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2),
val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2);
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS);
ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL);
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS),
vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL));
state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask;
ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask;
state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM));