drivers/gpu/drm/omapdrm/dss/dispc.c

835

dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));

drivers/gpu/drm/omapdrm/dss/dispc.c

836

dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));

drivers/gpu/drm/omapdrm/dss/dispc.c

837

dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));

drivers/gpu/drm/omapdrm/dss/dispc.c

838

dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));

drivers/gpu/drm/omapdrm/dss/dispc.c

839

dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));

drivers/gpu/drm/tidss/tidss_dispc.c

1554

regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1555

regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]);

drivers/gpu/drm/tidss/tidss_dispc.c

1556

regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]);

drivers/gpu/drm/tidss/tidss_dispc.c

1557

regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1558

regval[4] = CVAL(csc->m[CSC_BCB], 0);

drivers/gpu/drm/tidss/tidss_dispc.c

1566

regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1567

regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1568

regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]);

drivers/gpu/drm/tidss/tidss_dispc.c

1569

regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1570

regval[4] = CVAL(csc->m[CSC_CBB], 0);

drivers/gpu/drm/tidss/tidss_dispc.c

1578

regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1579

regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]);

drivers/gpu/drm/tidss/tidss_dispc.c

1580

regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]);

drivers/gpu/drm/tidss/tidss_dispc.c

1581

regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]);

drivers/gpu/drm/tidss/tidss_dispc.c

1582

regval[4] = CVAL(csc->m[CSC_BB], 0);

drivers/gpu/drm/tidss/tidss_dispc.c

2637

regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]);

drivers/gpu/drm/tidss/tidss_dispc.c

2638

regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]);

drivers/gpu/drm/tidss/tidss_dispc.c

2639

regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]);

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

666

dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

667

dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

668

dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

669

dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));

drivers/video/fbdev/omap2/omapfb/dss/dispc.c

670

dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));

fs/smb/client/smbencrypt.c

30

#define SSVALX(buf,pos,val) (CVAL(buf,pos)=(val)&0xFF,CVAL(buf,pos+1)=(val)>>8)