viafb_write_reg_mask
viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
viafb_write_reg_mask(CR96, VIACR, 0x03,
viafb_write_reg_mask(CR96, VIACR, 0x07,
viafb_write_reg_mask(CR96, VIACR, 0x07,
viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CR99, VIACR, 0x08,
viafb_write_reg_mask(CR99, VIACR, 0x0F,
viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
viafb_write_reg_mask(index, port, value, mask);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
viafb_write_reg_mask(CR96, VIACR,
viafb_write_reg_mask(SR1E, VIASR,
viafb_write_reg_mask(SR2A, VIASR,
viafb_write_reg_mask(SR1B, VIASR,
viafb_write_reg_mask(SR2A, VIASR,
viafb_write_reg_mask(CR9B, VIACR,
viafb_write_reg_mask(SR65, VIASR,
viafb_write_reg_mask(CR97, VIACR,
viafb_write_reg_mask(CR99, VIACR,
viafb_write_reg_mask(CR97, VIACR,
viafb_write_reg_mask(CR99, VIACR,
viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
viafb_write_reg_mask(CR99, VIACR, 0x08,
viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
viafb_write_reg_mask(CR97, VIACR, 0x84,
viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1);
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
viafb_write_reg_mask(CR96, VIACR,
viafb_write_reg_mask(SR2A, VIASR,
viafb_write_reg_mask(SR1B, VIASR,
viafb_write_reg_mask(SR2A, VIASR,
viafb_write_reg_mask(SR1E, VIASR,
viafb_write_reg_mask(CR9B, VIACR,
viafb_write_reg_mask(SR65, VIASR,
viafb_write_reg_mask(SR65, VIASR,
viafb_write_reg_mask(CR97, VIACR, reg_val, 0x0f);
viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f);