vgpu_vreg - Linux

drivers/gpu/drm/i915/gvt/cmd_parser.c

1033

vgpu_vreg(vgpu, offset) = data;

drivers/gpu/drm/i915/gvt/cmd_parser.c

961

vreg = &vgpu_vreg(s->vgpu, offset);

drivers/gpu/drm/i915/gvt/debugfs.c

68

vreg = vgpu_vreg(param->vgpu, offset);

drivers/gpu/drm/i915/gvt/display.c

55

u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);

drivers/gpu/drm/i915/gvt/display.c

81

if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))

drivers/gpu/drm/i915/gvt/edid.c

149

memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);

drivers/gpu/drm/i915/gvt/edid.c

151

pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;

drivers/gpu/drm/i915/gvt/edid.c

190

if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {

drivers/gpu/drm/i915/gvt/edid.c

192

vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;

drivers/gpu/drm/i915/gvt/edid.c

245

if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))

drivers/gpu/drm/i915/gvt/edid.c

279

vgpu_vreg(vgpu, offset) = wvalue;

drivers/gpu/drm/i915/gvt/edid.c

307

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

318

memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);

drivers/gpu/drm/i915/gvt/edid.c

319

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

340

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

349

u32 value = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/edid.c

351

if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))

drivers/gpu/drm/i915/gvt/edid.c

352

vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;

drivers/gpu/drm/i915/gvt/edid.c

363

vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;

drivers/gpu/drm/i915/gvt/edid.c

394

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/edid.c

428

memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);

drivers/gpu/drm/i915/gvt/edid.c

495

vgpu_vreg(vgpu, offset) = value;

drivers/gpu/drm/i915/gvt/edid.c

502

msg = vgpu_vreg(vgpu, offset + 4);

drivers/gpu/drm/i915/gvt/edid.c

513

vgpu_vreg(vgpu, offset) =

drivers/gpu/drm/i915/gvt/edid.c

562

vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;

drivers/gpu/drm/i915/gvt/execlist.c

117

vgpu_vreg(vgpu, status_reg) = status.ldw;

drivers/gpu/drm/i915/gvt/execlist.c

118

vgpu_vreg(vgpu, status_reg + 4) = status.udw;

drivers/gpu/drm/i915/gvt/execlist.c

139

ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);

drivers/gpu/drm/i915/gvt/execlist.c

152

vgpu_vreg(vgpu, offset) = status->ldw;

drivers/gpu/drm/i915/gvt/execlist.c

153

vgpu_vreg(vgpu, offset + 4) = status->udw;

drivers/gpu/drm/i915/gvt/execlist.c

156

vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;

drivers/gpu/drm/i915/gvt/execlist.c

262

status.ldw = vgpu_vreg(vgpu, status_reg);

drivers/gpu/drm/i915/gvt/execlist.c

263

status.udw = vgpu_vreg(vgpu, status_reg + 4);

drivers/gpu/drm/i915/gvt/execlist.c

516

ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);

drivers/gpu/drm/i915/gvt/execlist.c

519

vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;

drivers/gpu/drm/i915/gvt/execlist.c

98

status.ldw = vgpu_vreg(vgpu, status_reg);

drivers/gpu/drm/i915/gvt/execlist.c

99

status.udw = vgpu_vreg(vgpu, status_reg + 4);

drivers/gpu/drm/i915/gvt/handlers.c

1005

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1008

vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;

drivers/gpu/drm/i915/gvt/handlers.c

1018

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1021

vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;

drivers/gpu/drm/i915/gvt/handlers.c

1023

vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;

drivers/gpu/drm/i915/gvt/handlers.c

1039

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1061

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1083

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1086

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1089

if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)

drivers/gpu/drm/i915/gvt/handlers.c

109

memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

drivers/gpu/drm/i915/gvt/handlers.c

1139

vgpu_vreg(vgpu, reg) = value;

drivers/gpu/drm/i915/gvt/handlers.c

115

memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);

drivers/gpu/drm/i915/gvt/handlers.c

1203

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1219

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1227

msg = vgpu_vreg(vgpu, offset + 4);

drivers/gpu/drm/i915/gvt/handlers.c

1247

vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;

drivers/gpu/drm/i915/gvt/handlers.c

1264

u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);

drivers/gpu/drm/i915/gvt/handlers.c

1286

vgpu_vreg(vgpu, offset + 4) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1305

vgpu_vreg(vgpu, offset + 4) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1306

vgpu_vreg(vgpu, offset + 8) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1307

vgpu_vreg(vgpu, offset + 12) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1308

vgpu_vreg(vgpu, offset + 16) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1309

vgpu_vreg(vgpu, offset + 20) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1318

vgpu_vreg(vgpu, offset + 4 * idx) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1340

vgpu_vreg(vgpu, offset +

drivers/gpu/drm/i915/gvt/handlers.c

1373

vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;

drivers/gpu/drm/i915/gvt/handlers.c

1429

vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, sbi_offset);

drivers/gpu/drm/i915/gvt/handlers.c

1441

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1449

vgpu_vreg(vgpu, offset) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1607

if (vgpu_vreg(vgpu, offset) &

drivers/gpu/drm/i915/gvt/handlers.c

1609

vgpu_vreg(vgpu, offset) |=

drivers/gpu/drm/i915/gvt/handlers.c

1612

vgpu_vreg(vgpu, offset) &=

drivers/gpu/drm/i915/gvt/handlers.c

1622

if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)

drivers/gpu/drm/i915/gvt/handlers.c

1623

vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;

drivers/gpu/drm/i915/gvt/handlers.c

1625

vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;

drivers/gpu/drm/i915/gvt/handlers.c

1635

if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)

drivers/gpu/drm/i915/gvt/handlers.c

1636

vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;

drivers/gpu/drm/i915/gvt/handlers.c

1647

mode = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1688

if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1691

if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1694

if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1697

if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))

drivers/gpu/drm/i915/gvt/handlers.c

1700

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1818

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1831

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1844

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1857

vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1860

vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1861

vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;

drivers/gpu/drm/i915/gvt/handlers.c

1865

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1873

u32 v = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1877

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1888

vgpu_vreg(vgpu, offset - 0x600) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1889

vgpu_vreg(vgpu, offset - 0x800) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1891

vgpu_vreg(vgpu, offset - 0x400) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1892

vgpu_vreg(vgpu, offset - 0x600) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1895

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1920

vgpu_vreg(vgpu, offset) = v;

drivers/gpu/drm/i915/gvt/handlers.c

1928

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

1955

vgpu_vreg(vgpu, offset) = lower_32_bits(pat);

drivers/gpu/drm/i915/gvt/handlers.c

1966

vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;

drivers/gpu/drm/i915/gvt/handlers.c

1991

vgpu_vreg(vgpu, offset) =

drivers/gpu/drm/i915/gvt/handlers.c

2106

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

2138

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

2145

vgpu_vreg(vgpu, offset) = data;

drivers/gpu/drm/i915/gvt/handlers.c

303

old = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

3124

old_vreg = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

3126

mask = vgpu_vreg(vgpu, offset) >> 16;

drivers/gpu/drm/i915/gvt/handlers.c

3127

vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |

drivers/gpu/drm/i915/gvt/handlers.c

3128

(vgpu_vreg(vgpu, offset) & mask);

drivers/gpu/drm/i915/gvt/handlers.c

3185

old_vreg = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

3197

data |= vgpu_vreg(vgpu, offset) & ro_mask;

drivers/gpu/drm/i915/gvt/handlers.c

3203

u32 mask = vgpu_vreg(vgpu, offset) >> 16;

drivers/gpu/drm/i915/gvt/handlers.c

3205

vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)

drivers/gpu/drm/i915/gvt/handlers.c

3206

| (vgpu_vreg(vgpu, offset) & mask);

drivers/gpu/drm/i915/gvt/handlers.c

3239

intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));

drivers/gpu/drm/i915/gvt/handlers.c

326

vgpu_vreg(vgpu, offset) = new;

drivers/gpu/drm/i915/gvt/handlers.c

327

vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));

drivers/gpu/drm/i915/gvt/handlers.c

338

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

375

vgpu_vreg(vgpu, offset) = 0;

drivers/gpu/drm/i915/gvt/handlers.c

397

if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {

drivers/gpu/drm/i915/gvt/handlers.c

415

if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)

drivers/gpu/drm/i915/gvt/handlers.c

416

vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

418

vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

427

if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)

drivers/gpu/drm/i915/gvt/handlers.c

428

vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

430

vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

432

if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)

drivers/gpu/drm/i915/gvt/handlers.c

433

vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;

drivers/gpu/drm/i915/gvt/handlers.c

435

vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;

drivers/gpu/drm/i915/gvt/handlers.c

448

vgpu_vreg(vgpu, offset) = 1 << 17;

drivers/gpu/drm/i915/gvt/handlers.c

451

vgpu_vreg(vgpu, offset) = 0x3;

drivers/gpu/drm/i915/gvt/handlers.c

454

vgpu_vreg(vgpu, offset) = 0x2f << 16;

drivers/gpu/drm/i915/gvt/handlers.c

724

data = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

727

vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

731

vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/handlers.c

819

if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {

drivers/gpu/drm/i915/gvt/handlers.c

820

vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/handlers.c

822

vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/handlers.c

833

vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;

drivers/gpu/drm/i915/gvt/handlers.c

843

u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);

drivers/gpu/drm/i915/gvt/handlers.c

976

data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;

drivers/gpu/drm/i915/gvt/handlers.c

993

vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |

drivers/gpu/drm/i915/gvt/handlers.c

994

(vgpu_vreg(vgpu, offset) & sticky_mask);

drivers/gpu/drm/i915/gvt/handlers.c

995

vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);

drivers/gpu/drm/i915/gvt/interrupt.c

205

trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),

drivers/gpu/drm/i915/gvt/interrupt.c

206

(vgpu_vreg(vgpu, reg) ^ imr));

drivers/gpu/drm/i915/gvt/interrupt.c

208

vgpu_vreg(vgpu, reg) = imr;

drivers/gpu/drm/i915/gvt/interrupt.c

234

u32 virtual_ier = vgpu_vreg(vgpu, reg);

drivers/gpu/drm/i915/gvt/interrupt.c

246

vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;

drivers/gpu/drm/i915/gvt/interrupt.c

247

vgpu_vreg(vgpu, reg) |= ier;

drivers/gpu/drm/i915/gvt/interrupt.c

276

trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),

drivers/gpu/drm/i915/gvt/interrupt.c

277

(vgpu_vreg(vgpu, reg) ^ ier));

drivers/gpu/drm/i915/gvt/interrupt.c

279

vgpu_vreg(vgpu, reg) = ier;

drivers/gpu/drm/i915/gvt/interrupt.c

314

trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),

drivers/gpu/drm/i915/gvt/interrupt.c

315

(vgpu_vreg(vgpu, reg) ^ iir));

drivers/gpu/drm/i915/gvt/interrupt.c

320

vgpu_vreg(vgpu, reg) &= ~iir;

drivers/gpu/drm/i915/gvt/interrupt.c

354

u32 val = vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

356

& vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

386

vgpu_vreg(vgpu, isr) &= ~clear_bits;

drivers/gpu/drm/i915/gvt/interrupt.c

387

vgpu_vreg(vgpu, isr) |= set_bits;

drivers/gpu/drm/i915/gvt/interrupt.c

394

vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));

drivers/gpu/drm/i915/gvt/interrupt.c

476

if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

479

set_bit(bit, (void *)&vgpu_vreg(vgpu,

drivers/gpu/drm/i915/gvt/interrupt.c

531

if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &

drivers/gpu/drm/i915/gvt/interrupt.c

543

if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))

drivers/gpu/drm/i915/gvt/interrupt.c

544

& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))

drivers/gpu/drm/i915/gvt/interrupt.c

548

if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))

drivers/gpu/drm/i915/gvt/scheduler.c

282

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

drivers/gpu/drm/i915/gvt/scheduler.c

286

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

drivers/gpu/drm/i915/gvt/scheduler.c

290

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =