drivers/gpu/drm/i915/gvt/cmd_parser.c

1407

stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

drivers/gpu/drm/i915/gvt/cmd_parser.c

1408

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

drivers/gpu/drm/i915/gvt/cmd_parser.c

1411

stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &

drivers/gpu/drm/i915/gvt/cmd_parser.c

1413

tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1433

set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1436

set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1438

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1441

set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1443

set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1448

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;

drivers/gpu/drm/i915/gvt/display.c

198

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

204

vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=

drivers/gpu/drm/i915/gvt/display.c

206

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

207

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

208

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

drivers/gpu/drm/i915/gvt/display.c

209

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

drivers/gpu/drm/i915/gvt/display.c

213

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=

drivers/gpu/drm/i915/gvt/display.c

217

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

222

vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=

drivers/gpu/drm/i915/gvt/display.c

224

vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=

drivers/gpu/drm/i915/gvt/display.c

228

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=

drivers/gpu/drm/i915/gvt/display.c

233

vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=

drivers/gpu/drm/i915/gvt/display.c

236

vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

238

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

240

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

242

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

245

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;

drivers/gpu/drm/i915/gvt/display.c

246

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;

drivers/gpu/drm/i915/gvt/display.c

248

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));

drivers/gpu/drm/i915/gvt/display.c

249

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/display.c

251

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/display.c

253

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);

drivers/gpu/drm/i915/gvt/display.c

254

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);

drivers/gpu/drm/i915/gvt/display.c

256

vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

257

vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

265

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

266

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

274

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

drivers/gpu/drm/i915/gvt/display.c

275

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

drivers/gpu/drm/i915/gvt/display.c

276

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

drivers/gpu/drm/i915/gvt/display.c

277

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

drivers/gpu/drm/i915/gvt/display.c

278

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

drivers/gpu/drm/i915/gvt/display.c

282

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);

drivers/gpu/drm/i915/gvt/display.c

283

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=

drivers/gpu/drm/i915/gvt/display.c

285

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=

drivers/gpu/drm/i915/gvt/display.c

287

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=

drivers/gpu/drm/i915/gvt/display.c

289

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=

drivers/gpu/drm/i915/gvt/display.c

292

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=

drivers/gpu/drm/i915/gvt/display.c

296

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=

drivers/gpu/drm/i915/gvt/display.c

298

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=

drivers/gpu/drm/i915/gvt/display.c

300

vgpu_vreg_t(vgpu,

drivers/gpu/drm/i915/gvt/display.c

304

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

306

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

311

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

312

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);

drivers/gpu/drm/i915/gvt/display.c

313

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

315

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

317

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

319

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

322

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

326

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

328

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

330

vgpu_vreg_t(vgpu,

drivers/gpu/drm/i915/gvt/display.c

335

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

337

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

342

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

343

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);

drivers/gpu/drm/i915/gvt/display.c

344

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

346

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/display.c

348

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

350

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/display.c

353

vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

357

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

359

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/display.c

361

vgpu_vreg_t(vgpu,

drivers/gpu/drm/i915/gvt/display.c

366

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

368

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

375

vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |

drivers/gpu/drm/i915/gvt/display.c

383

vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

drivers/gpu/drm/i915/gvt/display.c

385

vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=

drivers/gpu/drm/i915/gvt/display.c

398

vgpu_vreg_t(vgpu, DPLL_CTRL1) =

drivers/gpu/drm/i915/gvt/display.c

400

vgpu_vreg_t(vgpu, DPLL_CTRL1) |=

drivers/gpu/drm/i915/gvt/display.c

402

vgpu_vreg_t(vgpu, LCPLL1_CTL) =

drivers/gpu/drm/i915/gvt/display.c

404

vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);

drivers/gpu/drm/i915/gvt/display.c

411

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);

drivers/gpu/drm/i915/gvt/display.c

412

vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;

drivers/gpu/drm/i915/gvt/display.c

413

vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;

drivers/gpu/drm/i915/gvt/display.c

414

vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;

drivers/gpu/drm/i915/gvt/display.c

415

vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;

drivers/gpu/drm/i915/gvt/display.c

419

vgpu_vreg_t(vgpu, DPLL_CTRL2) &=

drivers/gpu/drm/i915/gvt/display.c

421

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

423

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

425

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

426

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

429

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

434

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/display.c

436

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/display.c

439

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

440

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

441

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

445

vgpu_vreg_t(vgpu, DPLL_CTRL2) &=

drivers/gpu/drm/i915/gvt/display.c

447

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

449

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

451

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

452

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

455

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

460

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/display.c

462

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/display.c

465

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

466

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

467

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

471

vgpu_vreg_t(vgpu, DPLL_CTRL2) &=

drivers/gpu/drm/i915/gvt/display.c

473

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

475

vgpu_vreg_t(vgpu, DPLL_CTRL2) |=

drivers/gpu/drm/i915/gvt/display.c

477

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

478

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=

drivers/gpu/drm/i915/gvt/display.c

481

vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=

drivers/gpu/drm/i915/gvt/display.c

486

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=

drivers/gpu/drm/i915/gvt/display.c

488

vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=

drivers/gpu/drm/i915/gvt/display.c

491

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

492

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;

drivers/gpu/drm/i915/gvt/display.c

493

vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

501

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

drivers/gpu/drm/i915/gvt/display.c

506

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

509

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;

drivers/gpu/drm/i915/gvt/display.c

511

vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;

drivers/gpu/drm/i915/gvt/display.c

516

vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;

drivers/gpu/drm/i915/gvt/display.c

520

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

521

vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

522

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;

drivers/gpu/drm/i915/gvt/display.c

523

vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;

drivers/gpu/drm/i915/gvt/display.c

526

vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;

drivers/gpu/drm/i915/gvt/display.c

663

vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/display.c

698

vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

drivers/gpu/drm/i915/gvt/display.c

700

vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

702

vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

drivers/gpu/drm/i915/gvt/display.c

704

vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

706

vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;

drivers/gpu/drm/i915/gvt/display.c

707

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

713

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

716

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

719

vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

drivers/gpu/drm/i915/gvt/display.c

721

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

723

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

729

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

731

vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

drivers/gpu/drm/i915/gvt/display.c

734

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

736

vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

drivers/gpu/drm/i915/gvt/display.c

739

vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

drivers/gpu/drm/i915/gvt/display.c

741

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

743

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

749

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

drivers/gpu/drm/i915/gvt/display.c

751

vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

drivers/gpu/drm/i915/gvt/display.c

754

vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

drivers/gpu/drm/i915/gvt/display.c

756

vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

drivers/gpu/drm/i915/gvt/display.c

759

vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

drivers/gpu/drm/i915/gvt/display.c

761

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

drivers/gpu/drm/i915/gvt/display.c

763

vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

drivers/gpu/drm/i915/gvt/display.c

78

if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))

drivers/gpu/drm/i915/gvt/display.c

95

if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)

drivers/gpu/drm/i915/gvt/edid.c

136

vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;

drivers/gpu/drm/i915/gvt/edid.c

138

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

drivers/gpu/drm/i915/gvt/edid.c

170

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

drivers/gpu/drm/i915/gvt/edid.c

171

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;

drivers/gpu/drm/i915/gvt/edid.c

177

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;

drivers/gpu/drm/i915/gvt/edid.c

179

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

drivers/gpu/drm/i915/gvt/edid.c

206

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;

drivers/gpu/drm/i915/gvt/edid.c

207

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;

drivers/gpu/drm/i915/gvt/edid.c

255

vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

drivers/gpu/drm/i915/gvt/edid.c

267

vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;

drivers/gpu/drm/i915/gvt/edid.c

305

if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {

drivers/gpu/drm/i915/gvt/fb_decoder.c

161

u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;

drivers/gpu/drm/i915/gvt/fb_decoder.c

224

val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

258

plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;

drivers/gpu/drm/i915/gvt/fb_decoder.c

274

plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>

drivers/gpu/drm/i915/gvt/fb_decoder.c

277

plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &

drivers/gpu/drm/i915/gvt/fb_decoder.c

281

val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

356

val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

382

plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;

drivers/gpu/drm/i915/gvt/fb_decoder.c

393

val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c

399

plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));

drivers/gpu/drm/i915/gvt/fb_decoder.c

400

plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));

drivers/gpu/drm/i915/gvt/gtt.c

996

u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &

drivers/gpu/drm/i915/gvt/handlers.c

1039

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1041

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/handlers.c

1043

if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)

drivers/gpu/drm/i915/gvt/handlers.c

1061

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1063

if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)

drivers/gpu/drm/i915/gvt/handlers.c

1083

vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1084

vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;

drivers/gpu/drm/i915/gvt/handlers.c

1086

vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/gvt/handlers.c

1424

if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRRD) {

drivers/gpu/drm/i915/gvt/handlers.c

1427

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

drivers/gpu/drm/i915/gvt/handlers.c

1451

if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRWR) {

drivers/gpu/drm/i915/gvt/handlers.c

1454

sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));

drivers/gpu/drm/i915/gvt/handlers.c

1456

write_virtual_sbi_register(vgpu, sbi_offset, vgpu_vreg_t(vgpu, SBI_DATA));

drivers/gpu/drm/i915/gvt/handlers.c

1710

u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);

drivers/gpu/drm/i915/gvt/handlers.c

1906

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/handlers.c

1908

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=

drivers/gpu/drm/i915/gvt/handlers.c

1913

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/handlers.c

1915

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=

drivers/gpu/drm/i915/gvt/handlers.c

366

vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;

drivers/gpu/drm/i915/gvt/handlers.c

398

vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;

drivers/gpu/drm/i915/gvt/handlers.c

399

vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;

drivers/gpu/drm/i915/gvt/handlers.c

400

vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;

drivers/gpu/drm/i915/gvt/handlers.c

401

vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;

drivers/gpu/drm/i915/gvt/handlers.c

404

vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=

drivers/gpu/drm/i915/gvt/handlers.c

483

u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));

drivers/gpu/drm/i915/gvt/handlers.c

497

switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {

drivers/gpu/drm/i915/gvt/handlers.c

509

vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));

drivers/gpu/drm/i915/gvt/handlers.c

521

wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));

drivers/gpu/drm/i915/gvt/handlers.c

523

wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));

drivers/gpu/drm/i915/gvt/handlers.c

547

vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));

drivers/gpu/drm/i915/gvt/handlers.c

583

temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));

drivers/gpu/drm/i915/gvt/handlers.c

592

vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;

drivers/gpu/drm/i915/gvt/handlers.c

593

if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)

drivers/gpu/drm/i915/gvt/handlers.c

595

vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));

drivers/gpu/drm/i915/gvt/handlers.c

597

vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));

drivers/gpu/drm/i915/gvt/handlers.c

599

vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));

drivers/gpu/drm/i915/gvt/handlers.c

601

vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));

drivers/gpu/drm/i915/gvt/handlers.c

625

if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&

drivers/gpu/drm/i915/gvt/handlers.c

626

(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {

drivers/gpu/drm/i915/gvt/handlers.c

627

dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &

drivers/gpu/drm/i915/gvt/handlers.c

637

switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &

drivers/gpu/drm/i915/gvt/handlers.c

675

port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &

drivers/gpu/drm/i915/gvt/handlers.c

691

link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));

drivers/gpu/drm/i915/gvt/handlers.c

692

link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));

drivers/gpu/drm/i915/gvt/handlers.c

695

htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);

drivers/gpu/drm/i915/gvt/handlers.c

696

vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);

drivers/gpu/drm/i915/gvt/handlers.c

824

vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))

drivers/gpu/drm/i915/gvt/handlers.c

842

u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));

drivers/gpu/drm/i915/gvt/handlers.c

844

u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));

drivers/gpu/drm/i915/gvt/handlers.c

885

if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)

drivers/gpu/drm/i915/gvt/handlers.c

888

if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)

drivers/gpu/drm/i915/gvt/handlers.c

890

&& ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)

drivers/gpu/drm/i915/gvt/handlers.c

948

vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

954

vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;

drivers/gpu/drm/i915/gvt/handlers.c

958

vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=

drivers/gpu/drm/i915/gvt/handlers.c

979

vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);

drivers/gpu/drm/i915/gvt/mmio.c

260

vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;

drivers/gpu/drm/i915/gvt/mmio.c

263

vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;

drivers/gpu/drm/i915/gvt/mmio.c

266

vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;

drivers/gpu/drm/i915/gvt/mmio.c

269

vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=

drivers/gpu/drm/i915/gvt/mmio.c

271

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/mmio.c

273

vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/mmio.c

275

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=

drivers/gpu/drm/i915/gvt/mmio.c

277

vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=

drivers/gpu/drm/i915/gvt/mmio.c

279

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=

drivers/gpu/drm/i915/gvt/mmio.c

281

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=

drivers/gpu/drm/i915/gvt/mmio.c

284

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=

drivers/gpu/drm/i915/gvt/mmio.c

286

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=

drivers/gpu/drm/i915/gvt/mmio.c

289

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=

drivers/gpu/drm/i915/gvt/mmio.c

291

vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=

drivers/gpu/drm/i915/gvt/mmio.c

294

vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=

drivers/gpu/drm/i915/gvt/mmio_context.c

241

*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);

drivers/gpu/drm/i915/gvt/mmio_context.c

271

*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));

drivers/gpu/drm/i915/gvt/mmio_context.c

298

*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));

drivers/gpu/drm/i915/gvt/mmio_context.c

404

vgpu_vreg_t(vgpu, reg) = 0;

drivers/gpu/drm/i915/gvt/mmio_context.c

438

old_v = vgpu_vreg_t(pre, offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

442

new_v = vgpu_vreg_t(next, offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

456

old_v = vgpu_vreg_t(pre, l3_offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

460

new_v = vgpu_vreg_t(next, l3_offset);

drivers/gpu/drm/i915/gvt/mmio_context.c

511

vgpu_vreg_t(pre, mmio->reg) =

drivers/gpu/drm/i915/gvt/mmio_context.c

514

vgpu_vreg_t(pre, mmio->reg) &=

drivers/gpu/drm/i915/gvt/mmio_context.c

516

old_v = vgpu_vreg_t(pre, mmio->reg);

drivers/gpu/drm/i915/gvt/mmio_context.c

535

new_v = vgpu_vreg_t(next, mmio->reg) |

drivers/gpu/drm/i915/gvt/mmio_context.c

538

new_v = vgpu_vreg_t(next, mmio->reg);

drivers/gpu/drm/i915/gvt/scheduler.c

661

vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =

drivers/gpu/drm/i915/gvt/scheduler.c

980

vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;

drivers/gpu/drm/i915/gvt/scheduler.c

981

vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;

drivers/gpu/drm/i915/gvt/vgpu.c

48

vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;

drivers/gpu/drm/i915/gvt/vgpu.c

49

vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;

drivers/gpu/drm/i915/gvt/vgpu.c

50

vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;

drivers/gpu/drm/i915/gvt/vgpu.c

51

vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;

drivers/gpu/drm/i915/gvt/vgpu.c

53

vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;

drivers/gpu/drm/i915/gvt/vgpu.c

54

vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;

drivers/gpu/drm/i915/gvt/vgpu.c

55

vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;

drivers/gpu/drm/i915/gvt/vgpu.c

57

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =

drivers/gpu/drm/i915/gvt/vgpu.c

59

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =

drivers/gpu/drm/i915/gvt/vgpu.c

61

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =

drivers/gpu/drm/i915/gvt/vgpu.c

63

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =

drivers/gpu/drm/i915/gvt/vgpu.c

66

vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);

drivers/gpu/drm/i915/gvt/vgpu.c

68

vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;

drivers/gpu/drm/i915/gvt/vgpu.c

69

vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;