Symbol: vgpu_cfg_space
drivers/gpu/drm/i915/gvt/cfg_space.c
100
pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off])
drivers/gpu/drm/i915/gvt/cfg_space.c
131
memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
drivers/gpu/drm/i915/gvt/cfg_space.c
150
u8 old = vgpu_cfg_space(vgpu)[offset];
drivers/gpu/drm/i915/gvt/cfg_space.c
172
u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
drivers/gpu/drm/i915/gvt/cfg_space.c
190
vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
drivers/gpu/drm/i915/gvt/cfg_space.c
330
memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
drivers/gpu/drm/i915/gvt/cfg_space.c
334
vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =
drivers/gpu/drm/i915/gvt/cfg_space.c
336
vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =
drivers/gpu/drm/i915/gvt/cfg_space.c
341
gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);
drivers/gpu/drm/i915/gvt/cfg_space.c
347
vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
drivers/gpu/drm/i915/gvt/cfg_space.c
353
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
drivers/gpu/drm/i915/gvt/cfg_space.c
354
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
drivers/gpu/drm/i915/gvt/cfg_space.c
355
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
drivers/gpu/drm/i915/gvt/cfg_space.c
356
memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
drivers/gpu/drm/i915/gvt/cfg_space.c
363
memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
drivers/gpu/drm/i915/gvt/cfg_space.c
367
if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {
drivers/gpu/drm/i915/gvt/cfg_space.c
368
next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];
drivers/gpu/drm/i915/gvt/cfg_space.c
370
if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {
drivers/gpu/drm/i915/gvt/cfg_space.c
374
next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];
drivers/gpu/drm/i915/gvt/cfg_space.c
387
u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];
drivers/gpu/drm/i915/gvt/cfg_space.c
388
bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=
drivers/gpu/drm/i915/gvt/cfg_space.c
74
u8 *cfg_base = vgpu_cfg_space(vgpu);
drivers/gpu/drm/i915/gvt/gvt.h
479
pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
drivers/gpu/drm/i915/gvt/interrupt.c
434
control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset));
drivers/gpu/drm/i915/gvt/interrupt.c
435
addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));
drivers/gpu/drm/i915/gvt/interrupt.c
436
data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset));
drivers/gpu/drm/i915/gvt/opregion.c
445
if ((vgpu_cfg_space(vgpu)[INTEL_GVT_PCI_SWSCI]