ves1x93_writereg
ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);
ves1x93_writereg (state, 0, state->init_1x93_tab[0]);
return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);
return ves1x93_writereg (state, 0x0d, 0x08);
return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);
ves1x93_writereg (state, 0x06, 0xff & BDR);
ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));
ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));
ves1x93_writereg (state, 0x09, BDRI);
ves1x93_writereg (state, 0x20, ADCONF);
ves1x93_writereg (state, 0x21, FCONF);
ves1x93_writereg (state, 0x05, AGCR);
ves1x93_writereg (state, i, val);
return ves1x93_writereg (state, 0x1f, 0x20);
return ves1x93_writereg (state, 0x1f, 0x30);
return ves1x93_writereg (state, 0x1f, 0x00);
ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */
ves1x93_writereg (state, 0x18, 0x80); /* dto. */
return ves1x93_writereg (state, 0x00, 0x08);
return ves1x93_writereg(state, 0x00, 0x11);
return ves1x93_writereg(state, 0x00, 0x01);