arch/arm64/kvm/sys_regs.c

1413

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

1506

#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1507

#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1508

#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1509

#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1524

{ SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \

arch/arm64/kvm/sys_regs.c

1683

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

2614

.access = undef_access, \

arch/arm64/kvm/sys_regs.c

3230

{ SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },

arch/arm64/kvm/sys_regs.c

3387

{ SYS_DESC(SYS_TRFCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3388

{ SYS_DESC(SYS_SMPRI_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3389

{ SYS_DESC(SYS_SMCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3405

{ SYS_DESC(SYS_ICC_PMR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3431

{ SYS_DESC(SYS_PMSCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3432

{ SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3433

{ SYS_DESC(SYS_PMSICR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3434

{ SYS_DESC(SYS_PMSIRR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3435

{ SYS_DESC(SYS_PMSFCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3436

{ SYS_DESC(SYS_PMSEVFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3437

{ SYS_DESC(SYS_PMSLATFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3438

{ SYS_DESC(SYS_PMSIDR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3439

{ SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3440

{ SYS_DESC(SYS_PMBPTR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3441

{ SYS_DESC(SYS_PMBSR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3442

{ SYS_DESC(SYS_PMSDSFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3466

{ SYS_DESC(SYS_MPAMIDR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3469

{ SYS_DESC(SYS_MPAM1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3470

{ SYS_DESC(SYS_MPAM0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3471

{ SYS_DESC(SYS_MPAMSM_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3476

{ SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3477

{ SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3478

{ SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3479

{ SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3480

{ SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3481

{ SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3482

{ SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3483

{ SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3484

{ SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3485

{ SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3486

{ SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3487

{ SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3493

{ SYS_DESC(SYS_ICC_RPR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3497

{ SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3498

{ SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3499

{ SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3500

{ SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3501

{ SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3503

{ SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3504

{ SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3509

{ SYS_DESC(SYS_ACCDATA_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3511

{ SYS_DESC(SYS_SCXTNUM_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3526

{ SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },

arch/arm64/kvm/sys_regs.c

3527

{ SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },

arch/arm64/kvm/sys_regs.c

3575

{ SYS_DESC(SYS_TPIDR2_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3577

{ SYS_DESC(SYS_SCXTNUM_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3579

{ SYS_DESC(SYS_AMCR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3580

{ SYS_DESC(SYS_AMCFGR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3581

{ SYS_DESC(SYS_AMCGCR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3582

{ SYS_DESC(SYS_AMUSERENR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3583

{ SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3584

{ SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3585

{ SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3586

{ SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3767

{ SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },

arch/arm64/kvm/sys_regs.c

3786

{ SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },

arch/arm64/kvm/sys_regs.c

3791

{ SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },

arch/arm64/kvm/sys_regs.c

3804

{ SYS_DESC(SYS_MPAMHCR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3805

{ SYS_DESC(SYS_MPAMVPMV_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3806

{ SYS_DESC(SYS_MPAM2_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3807

{ SYS_DESC(SYS_MPAMVPM0_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3808

{ SYS_DESC(SYS_MPAMVPM1_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3809

{ SYS_DESC(SYS_MPAMVPM2_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3810

{ SYS_DESC(SYS_MPAMVPM3_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3811

{ SYS_DESC(SYS_MPAMVPM4_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3812

{ SYS_DESC(SYS_MPAMVPM5_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3813

{ SYS_DESC(SYS_MPAMVPM6_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3814

{ SYS_DESC(SYS_MPAMVPM7_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3817

{ SYS_DESC(SYS_RVBAR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3818

{ SYS_DESC(SYS_RMR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3944

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4037

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4062

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4116

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4141

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4175

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

4557

{ CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4607

{ CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4608

{ CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4609

{ CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4610

{ CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4611

{ CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4612

{ CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4613

{ CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4614

{ CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4615

{ CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4616

{ CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4617

{ CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4618

{ CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4620

{ CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4621

{ CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4622

{ CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4623

{ CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4624

{ CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4625

{ CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4627

{ CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4628

{ CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

4707

{ Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },

arch/arm64/kvm/sys_regs.c

527

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

609

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

655

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

66

return undef_access(vcpu, params, r);

arch/arm64/kvm/sys_regs.c

674

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

677

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

688

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

710

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

732

return undef_access(vcpu, p, r);

arch/arm64/kvm/sys_regs.c

789

return undef_access(vcpu, p, r);