vdpu_write_relaxed
vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6);
vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC);
vdpu_write_relaxed(vpu,
vdpu_write_relaxed(vpu, 0, G1_REG_REF_BUF_CTRL);
vdpu_write_relaxed(vpu, G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(8),
vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);
vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);
vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2));
vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++));
vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC);
vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++));
vdpu_write_relaxed(vpu, dma_addr, G1_REG_ADDR_REF(i));
vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR);
vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DST);
vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DIR_MV);
vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE);
vdpu_write_relaxed(vpu,
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4);
vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);
vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE);
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE);
vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER2_BASE);
vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER3_BASE);
vdpu_write_relaxed(vpu, reg, G1_SWREG(2));
vdpu_write_relaxed(vpu, reg, G1_SWREG(3));
vdpu_write_relaxed(vpu, reg, G1_SWREG(4));
vdpu_write_relaxed(vpu, reg, G1_SWREG(5));
vdpu_write_relaxed(vpu, reg, G1_SWREG(6));
vdpu_write_relaxed(vpu, reg, G1_SWREG(18));
vdpu_write_relaxed(vpu, reg, G1_SWREG(48));
vdpu_write_relaxed(vpu, reg, G1_SWREG(55));
vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE);
vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0));
vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK))
vdpu_write_relaxed(vpu,
vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0));
vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4));
vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(5));
vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma,
vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(0));
vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST);
vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2);
vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4);
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108));
vdpu_write_relaxed(vpu, dma_addr, VDPU_REG_REFER_BASE(i));
vdpu_write_relaxed(vpu, src_dma, VDPU_REG_RLC_VLC_BASE);
vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DEC_OUT_BASE);
vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DIR_MV_BASE);
vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE);
vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE);
vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE);
vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE);
vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER2_BASE);
vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));
vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE);
vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ);
vdpu_write_relaxed(vpu, (mb_offset_bytes & (~DEC_8190_ALIGN_MASK)) +
vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF0);
vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(2));
vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(3));
vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma,
vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_SEGMENT_VAL);
vdpu_write_relaxed(vpu, dst_dma, VDPU_REG_ADDR_DST);
vdpu_write_relaxed(vpu, reg, VDPU_REG_EN_FLAGS);
vdpu_write_relaxed(vpu, reg, VDPU_REG_DATA_ENDIAN);
vdpu_write_relaxed(vpu, reg, VDPU_REG_AXI_CTRL);
vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_FORMAT);
vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_DCT_START_BIT);