ufshcd_writel
ufshcd_writel(hba, val, REG_UFS_MCQ_CFG);
ufshcd_writel(hba, msg->address_lo, REG_UFS_ESILBA);
ufshcd_writel(hba, msg->address_hi, REG_UFS_ESIUBA);
ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),
ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),
ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),
ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
ufshcd_writel(hba, 1 << tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);
ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);
ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
ufshcd_writel(hba, INT_AGGR_ENABLE |
ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV);
ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1);
ufshcd_writel(hba, host->host_clk / 1000000, DWC_UFS_REG_HCLKDIV);
ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufshcd_writel(hba,
ufshcd_writel(hba, 0,
ufshcd_writel(hba,
ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
ufshcd_writel(hba, ICE_ALLOCATOR_TYPE, REG_UFS_MEM_ICE_CONFIG);
ufshcd_writel(hba, config, REG_UFS_MEM_ICE_NUM_CORE);
ufshcd_writel(hba, reg, REG_UFS_CFG1);
ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufshcd_writel(hba, curr_ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW, UFS_MEM_ICE_CFG);
ufshcd_writel(hba, reg_val, UFS_MEM_ICE_CFG);
ufshcd_writel(hba, value, reg);
ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV);
ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE);
ufshcd_writel(hba, tmp, reg);