drivers/ufs/core/ufs-mcq.c

447

ufshcd_rmwl(hba, MCQ_MODE_SELECT, MCQ_MODE_SELECT, REG_UFS_MEM_CFG);

drivers/ufs/core/ufs-mcq.c

454

ufshcd_rmwl(hba, MCQ_MODE_SELECT, 0, REG_UFS_MEM_CFG);

drivers/ufs/core/ufs-mcq.c

460

ufshcd_rmwl(hba, ESI_ENABLE, ESI_ENABLE, REG_UFS_MEM_CFG);

drivers/ufs/host/ufs-exynos.c

256

ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);

drivers/ufs/host/ufs-mediatek.c

2286

ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, 0, REG_UFS_MMIO_OPT_CTRL_0);

drivers/ufs/host/ufs-mediatek.c

2297

ufshcd_rmwl(hba, MCQ_AH8, MCQ_AH8, REG_UFS_MMIO_OPT_CTRL_0);

drivers/ufs/host/ufs-mediatek.c

2298

ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, MCQ_MULTI_INTR_EN, REG_UFS_MMIO_OPT_CTRL_0);

drivers/ufs/host/ufs-mediatek.c

287

ufshcd_rmwl(hba, UFS_MASK(0x7FFF, 8),

drivers/ufs/host/ufs-mediatek.c

293

ufshcd_rmwl(hba, MRTT_EN, MRTT_EN, REG_UFS_MMIO_OPT_CTRL_0);

drivers/ufs/host/ufs-mediatek.c

295

ufshcd_rmwl(hba, RDN_PFM_IMPV_DIS, 0, REG_UFS_MMIO_OPT_CTRL_0);

drivers/ufs/host/ufs-qcom.c

1958

ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,

drivers/ufs/host/ufs-qcom.c

1960

ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);

drivers/ufs/host/ufs-qcom.c

2051

ufshcd_rmwl(host->hba, TEST_BUS_SEL,

drivers/ufs/host/ufs-qcom.c

2054

ufshcd_rmwl(host->hba, mask,

drivers/ufs/host/ufs-qcom.c

2179

ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);

drivers/ufs/host/ufs-qcom.c

2446

ufshcd_rmwl(hba, ESI_VEC_MASK, FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),

drivers/ufs/host/ufs-qcom.c

427

ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);

drivers/ufs/host/ufs-qcom.c

430

ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);

drivers/ufs/host/ufs-qcom.c

564

ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,

drivers/ufs/host/ufs-qcom.c

711

ufshcd_rmwl(hba, UFS_HW_CLK_CTRL_EN, UFS_HW_CLK_CTRL_EN,

drivers/ufs/host/ufs-qcom.h

295

ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1);

drivers/ufs/host/ufs-qcom.h

306

ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1);