ufshcd_readl
val = ufshcd_readl(hba, REG_UFS_MCQ_CFG);
ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
*val = ufshcd_readl(hba, reg);
cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
cpu_to_le32(ufshcd_readl(hba,
return ufshcd_readl(hba, REG_UFS_VERSION);
return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
ufshcd_readl(hba, REG_UTP_TASK_REQ_LIST_BASE_H);
ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
regs[pos / 4] = ufshcd_readl(hba, offset + pos);
hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
arg1 = ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1);
arg2 = ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2);
arg3 = ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
cmd->argument2 |= ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
cmd->argument3 = ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
last_intr_status = intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
enabled_intr_status = intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
return read_poll_timeout(ufshcd_readl, v, (v & mask) == val,
reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
ufshcd_readl(hba, CDNS_UFS_REG_HCLKDIV);
data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1);
if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) &
mbox = ufshcd_readl(hba, PH2VH_MBOX);
enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
val = ufshcd_readl(hba, REG_UFS_PROBE);
val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
val = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
(ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) & ~0x100),
ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
val = ufshcd_readl(hba, REG_UFS_PROBE);
val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
val = ufshcd_readl(hba, REG_UFS_PROBE);
val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
ufshcd_readl(hba,
hw_ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
cap.reg_val = cpu_to_le32(ufshcd_readl(hba,
dev_err(hba->dev, "HW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_ENTER_CNT));
dev_err(hba->dev, "HW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_HW_H8_EXIT_CNT));
dev_err(hba->dev, "SW_H8_ENTER_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_ENTER_CNT));
dev_err(hba->dev, "SW_H8_EXIT_CNT=%d\n", ufshcd_readl(hba, REG_UFS_SW_H8_EXIT_CNT));
ufshcd_readl(hba, REG_UFS_SW_AFTER_HW_H8_ENTER_CNT));
reg = ufshcd_readl(hba, REG_UFS_CFG1);
curr_ahit = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
ufshcd_readl(hba, REG_UFS_CFG2);
if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
reg_val = ufshcd_readl(hba, UFS_MEM_ICE_CFG);
ufshcd_readl(hba, UFS_MEM_ICE_CFG);
u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
ufshcd_readl(hba, REG_UFS_CFG1);
ufshcd_readl(hba, REG_UFS_CFG1);
return ufshcd_readl(hba, reg);
val = ufshcd_readl(hba, REG_CONTROLLER_ENABLE);
u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE);
tmp = ufshcd_readl(hba, reg);