drivers/gpu/drm/i915/gt/intel_execlists_submission.c

1987

regs[CTX_RING_START],

drivers/gpu/drm/i915/gt/intel_lrc.c

1547

regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);

drivers/gpu/drm/i915/gt/intel_lrc.c

1591

if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {

drivers/gpu/drm/i915/gt/intel_lrc.c

1594

regs[CTX_RING_START],

drivers/gpu/drm/i915/gt/intel_lrc.c

1596

regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1638

if (ctx_bb[CTX_BB_CANARY_INDEX] == ce->lrc_reg_state[CTX_RING_START])

drivers/gpu/drm/i915/gt/selftest_lrc.c

1643

ce->lrc_reg_state[CTX_RING_START]);

drivers/gpu/drm/i915/gt/selftest_lrc.c

306

CTX_RING_START - 1,

drivers/gpu/drm/xe/xe_lrc.c

1552

xe_lrc_write_ctx_reg(lrc, CTX_RING_START, __xe_lrc_ring_ggtt_addr(lrc));

drivers/gpu/drm/xe/xe_lrc.c

1763

xe_lrc_write_ctx_reg(lrc, CTX_RING_START, __xe_lrc_ring_ggtt_addr(lrc));

drivers/gpu/drm/xe/xe_lrc.c

1788

return xe_lrc_read_ctx_reg(lrc, CTX_RING_START);