vcpu_get_reg
u64 val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu));
vcpu_set_reg(vcpu, i, (u32)vcpu_get_reg(vcpu, i));
val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu));
trace_kvm_hvc_arm64(*vcpu_pc(vcpu), vcpu_get_reg(vcpu, 0),
u64 val = vcpu_get_reg(vcpu, rt);
u64 val = vcpu_get_reg(vcpu, rt);
params.regval = vcpu_get_reg(vcpu, Rt);
u32 data = vcpu_get_reg(vcpu, rd);
u32 val = vcpu_get_reg(vcpu, rt);
u32 val = vcpu_get_reg(vcpu, rt);
u32 vid = vcpu_get_reg(vcpu, rt);
u32 vid = vcpu_get_reg(vcpu, rt);
u64 val = vcpu_get_reg(vcpu, rt);
u64 val = vcpu_get_reg(vcpu, rt);
u64 val = vcpu_get_reg(vcpu, rt);
u64 val = vcpu_get_reg(vcpu, rt);
u32 val = vcpu_get_reg(vcpu, rt);
val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu));
vcpu_write_sys_reg(vcpu, vcpu_get_reg(vcpu, rt), CPTR_EL2);
data = vcpu_data_guest_to_host(vcpu, vcpu_get_reg(vcpu, rt),
vcpu_set_reg(vcpu, i, lower_32_bits(vcpu_get_reg(vcpu, i)));
params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
params->regval = vcpu_get_reg(vcpu, Rt);
params.regval = vcpu_get_reg(vcpu, Rt);
return vcpu_get_reg(vcpu, 0);
return vcpu_get_reg(vcpu, 1);
return vcpu_get_reg(vcpu, 2);
return vcpu_get_reg(vcpu, 3);
val = vcpu_get_reg(vcpu, reg_id);
val = vcpu_get_reg(vcpu, reg_id);
val = vcpu_get_reg(vcpu, reg_id);
val = vcpu_get_reg(vcpu, reg_id);
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
aa64dfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
pfr1 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
u64 pfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
val = vcpu_get_reg(vcpu, reg_info->reg);
val = vcpu_get_reg(vcpu, reg_info->reg);
val = vcpu_get_reg(vcpu, reg_info->reg);
mmfr2 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR2_EL1));
pfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
obs_pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
obs_x0 = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0]));
target_mpidr = vcpu_get_reg(target, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1));
psci_version = vcpu_get_reg(target, KVM_REG_ARM_PSCI_VERSION);
val = vcpu_get_reg(vcpu, reg);
new_val = vcpu_get_reg(vcpu, reg);
val = vcpu_get_reg(vcpu, reg);
val = vcpu_get_reg(vcpu, reg);
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id));
observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
dfr0 = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
prev = get_pmcr_n(vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0)));
sp = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1));
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));
pmcr = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));
sctlr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1));
tcr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1));
pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate));
pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
max_satp_mode = vcpu_get_reg(vcpu, RISCV_CONFIG_REG(satp_mode));
core.mode = vcpu_get_reg(vcpu, RISCV_CORE_REG(mode));
core.regs.pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc));
core.regs.ra = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra));
core.regs.sp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp));
core.regs.gp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp));
core.regs.tp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp));
core.regs.t0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0));
core.regs.t1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1));
core.regs.t2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2));
core.regs.s0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0));
core.regs.s1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1));
core.regs.a0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0));
core.regs.a1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1));
core.regs.a2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2));
core.regs.a3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3));
core.regs.a4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4));
core.regs.a5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5));
core.regs.a6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6));
core.regs.a7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7));
core.regs.s2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2));
core.regs.s3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3));
core.regs.s4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4));
core.regs.s5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5));
core.regs.s6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6));
core.regs.s7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7));
core.regs.s8 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8));
core.regs.s9 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9));
core.regs.s10 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10));
core.regs.s11 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11));
core.regs.t3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3));
core.regs.t4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4));
core.regs.t5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5));
core.regs.t6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6));
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)) + 4);
timer_freq = vcpu_get_reg(vcpus[0], RISCV_TIMER_REG(frequency));
pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc));
vlenb_reg = vcpu_get_reg(vcpu, s->regs[KVM_RISC_V_REG_OFFSET_VLENB]);
timer_freq = vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency));
eval_reg = vcpu_get_reg(vcpu, id);
unsigned long enabled = vcpu_get_reg(vcpu, id);
val = vcpu_get_reg(vcpu, KVM_X86_REG_KVM(reg));
val = vcpu_get_reg(vcpu, KVM_X86_REG_KVM(reg));
val = vcpu_get_reg(vcpu, KVM_X86_REG_MSR(msr));