drivers/gpu/drm/vc4/tests/vc4_mock.h

28

struct vc4_crtc crtc;

drivers/gpu/drm/vc4/tests/vc4_mock_crtc.c

26

struct vc4_crtc *vc4_crtc;

drivers/gpu/drm/vc4/tests/vc4_mock_crtc.c

32

vc4_crtc = &dummy_crtc->crtc;

drivers/gpu/drm/vc4/tests/vc4_mock_crtc.c

34

vc4_crtc, data, plane,

drivers/gpu/drm/vc4/vc4_crtc.c

115

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

1158

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

1159

const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

1162

&vc4_crtc->regset);

drivers/gpu/drm/vc4/vc4_crtc.c

1352

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

1353

const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

1395

struct vc4_crtc *vc4_crtc,

drivers/gpu/drm/vc4/vc4_crtc.c

1403

struct drm_crtc *crtc = &vc4_crtc->base;

drivers/gpu/drm/vc4/vc4_crtc.c

1407

vc4_crtc->data = data;

drivers/gpu/drm/vc4/vc4_crtc.c

1408

vc4_crtc->pdev = pdev;

drivers/gpu/drm/vc4/vc4_crtc.c

1409

vc4_crtc->feeds_txp = feeds_txp;

drivers/gpu/drm/vc4/vc4_crtc.c

1410

spin_lock_init(&vc4_crtc->irq_lock);

drivers/gpu/drm/vc4/vc4_crtc.c

1419

drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));

drivers/gpu/drm/vc4/vc4_crtc.c

1429

vc4_crtc->lut_r[i] = i;

drivers/gpu/drm/vc4/vc4_crtc.c

1430

vc4_crtc->lut_g[i] = i;

drivers/gpu/drm/vc4/vc4_crtc.c

1431

vc4_crtc->lut_b[i] = i;

drivers/gpu/drm/vc4/vc4_crtc.c

1438

struct vc4_crtc *vc4_crtc,

drivers/gpu/drm/vc4/vc4_crtc.c

1458

return __vc4_crtc_init(drm, pdev, vc4_crtc, data, primary_plane,

drivers/gpu/drm/vc4/vc4_crtc.c

1467

struct vc4_crtc *vc4_crtc;

drivers/gpu/drm/vc4/vc4_crtc.c

1471

vc4_crtc = drmm_kzalloc(drm, sizeof(*vc4_crtc), GFP_KERNEL);

drivers/gpu/drm/vc4/vc4_crtc.c

1472

if (!vc4_crtc)

drivers/gpu/drm/vc4/vc4_crtc.c

1474

crtc = &vc4_crtc->base;

drivers/gpu/drm/vc4/vc4_crtc.c

1480

vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);

drivers/gpu/drm/vc4/vc4_crtc.c

1481

if (IS_ERR(vc4_crtc->regs))

drivers/gpu/drm/vc4/vc4_crtc.c

1482

return PTR_ERR(vc4_crtc->regs);

drivers/gpu/drm/vc4/vc4_crtc.c

1484

vc4_crtc->regset.base = vc4_crtc->regs;

drivers/gpu/drm/vc4/vc4_crtc.c

1485

vc4_crtc->regset.regs = crtc_regs;

drivers/gpu/drm/vc4/vc4_crtc.c

1486

vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);

drivers/gpu/drm/vc4/vc4_crtc.c

1488

ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base,

drivers/gpu/drm/vc4/vc4_crtc.c

1500

"vc4 crtc", vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

1504

platform_set_drvdata(pdev, vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

1513

struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);

drivers/gpu/drm/vc4/vc4_crtc.c

212

*stime = vc4_crtc->t_vblank;

drivers/gpu/drm/vc4/vc4_crtc.c

214

*etime = vc4_crtc->t_vblank;

drivers/gpu/drm/vc4/vc4_crtc.c

238

static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)

drivers/gpu/drm/vc4/vc4_crtc.c

240

const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

241

const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

242

struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);

drivers/gpu/drm/vc4/vc4_crtc.c

296

static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,

drivers/gpu/drm/vc4/vc4_crtc.c

299

u32 level = vc4_get_fifo_full_level(vc4_crtc, format);

drivers/gpu/drm/vc4/vc4_crtc.c

331

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

351

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

352

const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

377

struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);

drivers/gpu/drm/vc4/vc4_crtc.c

378

dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",

drivers/gpu/drm/vc4/vc4_crtc.c

380

drm_print_regset32(&p, &vc4_crtc->regset);

drivers/gpu/drm/vc4/vc4_crtc.c

468

vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |

drivers/gpu/drm/vc4/vc4_crtc.c

478

struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);

drivers/gpu/drm/vc4/vc4_crtc.c

479

dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",

drivers/gpu/drm/vc4/vc4_crtc.c

481

drm_print_regset32(&p, &vc4_crtc->regset);

drivers/gpu/drm/vc4/vc4_crtc.c

504

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

553

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

562

if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,

drivers/gpu/drm/vc4/vc4_crtc.c

564

of_device_is_compatible(vc4_crtc->pdev->dev.of_node,

drivers/gpu/drm/vc4/vc4_crtc.c

566

of_device_is_compatible(vc4_crtc->pdev->dev.of_node,

drivers/gpu/drm/vc4/vc4_crtc.c

568

of_device_is_compatible(vc4_crtc->pdev->dev.of_node,

drivers/gpu/drm/vc4/vc4_crtc.c

57

writel(val, vc4_crtc->regs + (offset)); \

drivers/gpu/drm/vc4/vc4_crtc.c

578

channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);

drivers/gpu/drm/vc4/vc4_crtc.c

586

pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

63

readl(vc4_crtc->regs + (offset)); \

drivers/gpu/drm/vc4/vc4_crtc.c

656

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

794

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

810

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_crtc.c

822

static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)

drivers/gpu/drm/vc4/vc4_crtc.c

824

struct drm_crtc *crtc = &vc4_crtc->base;

drivers/gpu/drm/vc4/vc4_crtc.c

829

u32 chan = vc4_crtc->current_hvs_channel;

drivers/gpu/drm/vc4/vc4_crtc.c

833

spin_lock(&vc4_crtc->irq_lock);

drivers/gpu/drm/vc4/vc4_crtc.c

841

if (vc4_crtc->event &&

drivers/gpu/drm/vc4/vc4_crtc.c

842

(vc4_crtc->current_dlist == current_dlist || vc4_crtc->feeds_txp)) {

drivers/gpu/drm/vc4/vc4_crtc.c

843

drm_crtc_send_vblank_event(crtc, vc4_crtc->event);

drivers/gpu/drm/vc4/vc4_crtc.c

844

vc4_crtc->event = NULL;

drivers/gpu/drm/vc4/vc4_crtc.c

856

spin_unlock(&vc4_crtc->irq_lock);

drivers/gpu/drm/vc4/vc4_crtc.c

860

void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)

drivers/gpu/drm/vc4/vc4_crtc.c

869

struct vc4_crtc *vc4_crtc = data;

drivers/gpu/drm/vc4/vc4_crtc.c

875

vc4_crtc_handle_vblank(vc4_crtc);

drivers/gpu/drm/vc4/vc4_drv.h

600

container_of_const(_crtc, struct vc4_crtc, base)

drivers/gpu/drm/vc4/vc4_drv.h

603

vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)

drivers/gpu/drm/vc4/vc4_drv.h

609

vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)

drivers/gpu/drm/vc4/vc4_drv.h

935

struct vc4_crtc *vc4_crtc, const struct vc4_crtc_data *data,

drivers/gpu/drm/vc4/vc4_drv.h

941

struct vc4_crtc *vc4_crtc, const struct vc4_crtc_data *data,

drivers/gpu/drm/vc4/vc4_drv.h

956

void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

1036

vc4_hvs_update_gamma_lut(hvs, vc4_crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

421

struct vc4_crtc *vc4_crtc)

drivers/gpu/drm/vc4/vc4_hvs.c

425

struct drm_crtc *crtc = &vc4_crtc->base;

drivers/gpu/drm/vc4/vc4_hvs.c

447

HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);

drivers/gpu/drm/vc4/vc4_hvs.c

449

HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);

drivers/gpu/drm/vc4/vc4_hvs.c

451

HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);

drivers/gpu/drm/vc4/vc4_hvs.c

458

struct vc4_crtc *vc4_crtc)

drivers/gpu/drm/vc4/vc4_hvs.c

460

struct drm_crtc_state *crtc_state = vc4_crtc->base.state;

drivers/gpu/drm/vc4/vc4_hvs.c

466

vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);

drivers/gpu/drm/vc4/vc4_hvs.c

467

vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);

drivers/gpu/drm/vc4/vc4_hvs.c

468

vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);

drivers/gpu/drm/vc4/vc4_hvs.c

471

vc4_hvs_lut_load(hvs, vc4_crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

624

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

677

vc4_hvs_lut_load(hvs, vc4_crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

860

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

871

if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) {

drivers/gpu/drm/vc4/vc4_hvs.c

872

vc4_crtc->event = crtc->state->event;

drivers/gpu/drm/vc4/vc4_hvs.c

879

spin_lock_irqsave(&vc4_crtc->irq_lock, flags);

drivers/gpu/drm/vc4/vc4_hvs.c

880

vc4_crtc->current_dlist = vc4_state->mm.start;

drivers/gpu/drm/vc4/vc4_hvs.c

881

spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);

drivers/gpu/drm/vc4/vc4_hvs.c

887

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

891

spin_lock_irqsave(&vc4_crtc->irq_lock, flags);

drivers/gpu/drm/vc4/vc4_hvs.c

892

vc4_crtc->current_hvs_channel = vc4_state->assigned_channel;

drivers/gpu/drm/vc4/vc4_hvs.c

893

spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);

drivers/gpu/drm/vc4/vc4_hvs.c

902

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_hvs.c

903

bool oneshot = vc4_crtc->feeds_txp;

drivers/gpu/drm/vc4/vc4_hvs.c

934

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_kms.c

222

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_kms.c

243

if (vc4_crtc->feeds_txp)

drivers/gpu/drm/vc4/vc4_kms.c

268

struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_kms.c

274

switch (vc4_crtc->data->hvs_output) {

drivers/gpu/drm/vc4/vc4_kms.c

833

const struct vc4_crtc *crtc_a =

drivers/gpu/drm/vc4/vc4_kms.c

837

const struct vc4_crtc *crtc_b =

drivers/gpu/drm/vc4/vc4_kms.c

927

struct vc4_crtc *vc4_crtc;

drivers/gpu/drm/vc4/vc4_kms.c

934

vc4_crtc = to_vc4_crtc(crtc);

drivers/gpu/drm/vc4/vc4_kms.c

974

matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;

drivers/gpu/drm/vc4/vc4_txp.c

165

struct vc4_crtc base;

drivers/gpu/drm/vc4/vc4_txp.c

495

struct vc4_crtc *vc4_crtc = &txp->base;

drivers/gpu/drm/vc4/vc4_txp.c

508

vc4_crtc_handle_vblank(vc4_crtc);

drivers/gpu/drm/vc4/vc4_txp.c

559

struct vc4_crtc *vc4_crtc;

drivers/gpu/drm/vc4/vc4_txp.c

581

vc4_crtc = &txp->base;

drivers/gpu/drm/vc4/vc4_txp.c

582

vc4_crtc->regset.base = txp->regs;

drivers/gpu/drm/vc4/vc4_txp.c

583

vc4_crtc->regset.regs = txp_regs;

drivers/gpu/drm/vc4/vc4_txp.c

584

vc4_crtc->regset.nregs = ARRAY_SIZE(txp_regs);

drivers/gpu/drm/vc4/vc4_txp.c

586

ret = vc4_crtc_init(drm, pdev, vc4_crtc, &txp_data->base,

drivers/gpu/drm/vc4/vc4_txp.c

595

encoder->possible_crtcs = drm_crtc_mask(&vc4_crtc->base);