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CVMX_CIU_PP_RST
arch/mips/cavium-octeon/smp.c
339
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
arch/mips/cavium-octeon/smp.c
340
cvmx_write_csr(CVMX_CIU_PP_RST, 0);
arch/mips/cavium-octeon/smp.c
388
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
arch/mips/cavium-octeon/smp.c
389
cvmx_write_csr(CVMX_CIU_PP_RST, 0);