arch/mips/cavium-octeon/executive/cvmx-l2c.c

309

len -= CVMX_CACHE_LINE_SIZE;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

310

ptr += CVMX_CACHE_LINE_SIZE;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

394

fault_in(addr, CVMX_CACHE_LINE_SIZE);

arch/mips/cavium-octeon/executive/cvmx-l2c.c

425

start += CVMX_CACHE_LINE_SIZE;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

426

len -= CVMX_CACHE_LINE_SIZE;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

515

start += CVMX_CACHE_LINE_SIZE;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

516

len -= CVMX_CACHE_LINE_SIZE;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

764

CVMX_CACHE_LINE_SIZE;

arch/mips/cavium-octeon/executive/cvmx-l2c.c

911

index * CVMX_CACHE_LINE_SIZE),

arch/mips/include/asm/octeon/cvmx-config.h

24

#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx-config.h

25

#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx-config.h

26

#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx-config.h

27

#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx-config.h

28

#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx-config.h

29

#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx-config.h

30

#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx-config.h

31

#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)

arch/mips/include/asm/octeon/cvmx.h

88

#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */

arch/mips/include/asm/octeon/cvmx.h

89

#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))

drivers/mmc/host/cavium-octeon.c

65

end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);

drivers/mmc/host/cavium-octeon.c

66

start = ALIGN(start, CVMX_CACHE_LINE_SIZE);

drivers/mmc/host/cavium-octeon.c

70

start += CVMX_CACHE_LINE_SIZE;

drivers/mmc/host/cavium-octeon.c

81

end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);

drivers/mmc/host/cavium-octeon.c

82

start = ALIGN(start, CVMX_CACHE_LINE_SIZE);

drivers/mmc/host/cavium-octeon.c

86

start += CVMX_CACHE_LINE_SIZE;