v9
.ifc \vxr,%v9
struct atom_vram_module_v9 v9;
((u8 *)vram_module + vram_module->v9.vram_module_size);
mem_type = vram_module->v9.memory_type;
mem_channel_number = vram_module->v9.channel_num;
mem_channel_width = vram_module->v9.channel_width;
mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
((u8 *)vram_module + vram_module->v9.vram_module_size);
mem_type = vram_module->v9.memory_type;
mem_channel_number = vram_module->v9.channel_num;
mem_channel_width = vram_module->v9.channel_width;
mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
v5, f6, v6, f7, v7, f8, v8, f9, v9) \
FN(reg, f9), v9)
v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
FN(reg, f9), v9, \
#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \
FN(reg, f9), v9)
#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
FN(reg, f9), v9, \
#define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
FN(reg, f9), v9, \
#define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
FN(reg, f9), v9, \
#define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
FN(reg, f9), v9, \
struct iwl_dev_tx_power_cmd_v9 v9;
} v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */
len = sizeof(cmd_v9_v10.v9);
per_chain = &cmd_v9_v10.v9.per_chain[0][0];
len = sizeof(cmd_v9_v10.v9);
cmd->v9.adwell_default_hb_n_aps =
if (VERSION_LT(e->version, v5) || VERSION_GT(e->version, v9)) {
CHECK_VECTOR_REGISTER(v9);