v8
u8 v8;
rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
.ifc \vxr,%v8
u8 v8;
v8 = __raw_readb(DACR);
v8 &= ~DACR_DAE;
__raw_writeb(v8,DACR);
v8 = __raw_readb(SCPDR);
v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y;
v8 &= ~SCPDR_TS_SCAN_ENABLE;
__raw_writeb(v8, SCPDR);
u8 v8;
v8 = inb(PKDR);
v8 &= ~PKDR_SPEAKER;
outb(v8, PKDR);
u8 v8;
v8 = inb(PKDR);
v8 |= PKDR_SPEAKER;
outb(v8, PKDR);
u8 v8;
pci_read_config_byte(sonypi_device.dev, SONYPI_TYPE3_MISC, &v8);
v8 = (v8 & 0xCF) | 0x10;
pci_write_config_byte(sonypi_device.dev, SONYPI_TYPE3_MISC, v8);
f5, v5, f6, v6, f7, v7, f8, v8) \
FN(reg, f8), v8)
v5, f6, v6, f7, v7, f8, v8, f9, v9) \
FN(reg, f8), v8, \
v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
FN(reg, f8), v8, \
#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
FN(reg_name, f8), v8)
#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
FN(reg, f8), v8)
#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \
FN(reg, f8), v8, \
#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
FN(reg, f8), v8, \
#define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
FN(reg, f8), v8, \
#define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
FN(reg, f8), v8, \
#define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
FN(reg, f8), v8, \
u8 v8;
v8 = inb(PKDR);
outb(v8 & (~PKDR_LED_GREEN), PKDR);
outb(v8 | PKDR_LED_GREEN, PKDR);
struct iwl_dev_tx_power_cmd_v8 v8;
} v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */
len = sizeof(cmd.v8);
per_chain = cmd.v8.per_chain[0][0];
cmd.v8.flags = cpu_to_le32(mvm->fwrt.reduced_power_flags);
len = sizeof(cmd.v8);
return (void *)&cmd->v8.data;
return &cmd->v8.channel;
cmd->v8.active_dwell[SCAN_LB_LMAC_IDX] = active_dwell;
cmd->v8.passive_dwell[SCAN_LB_LMAC_IDX] = passive_dwell;
cmd->v8.active_dwell[SCAN_HB_LMAC_IDX] =
cmd->v8.passive_dwell[SCAN_HB_LMAC_IDX] =
cmd->v8.num_of_fragments[SCAN_LB_LMAC_IDX] =
cmd->v8.num_of_fragments[SCAN_HB_LMAC_IDX] =
cmd->v8.general_flags2 =
prptctrl = &pfwinfo->rpt_ctrl.finfo.v8;
pfinfo = &pfwinfo->rpt_ctrl.finfo.v8;
pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo.v8);
fwsubver->fcxbtcrpt = pfwinfo->rpt_ctrl.finfo.v8.fver;
prpt->v8 = pfwinfo->rpt_ctrl.finfo.v8;
pfwinfo->rpt_en_map = le32_to_cpu(prpt->v8.rpt_info.en);
wl->ver_info.fw_coex = le32_to_cpu(prpt->v8.rpt_info.cx_ver);
wl->ver_info.fw = le32_to_cpu(prpt->v8.rpt_info.fw_ver);
memcpy(&dm->gnt.band[i], &prpt->v8.gnt_val[i][0],
le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_HI_TX_V105]);
le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_HI_RX_V105]);
le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_LO_TX_V105]);
le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_LO_RX_V105]);
val1 = le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_POLLUTED_V105]);
le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_POLLUTED_V105]);
if (((prpt->v8.rpt_len_max_h << 8) +
prpt->v8.rpt_len_max_l) != ver->info_buf)
r.v8.type = SET_REPORT_EN;
r.v8.fver = btc->ver->fcxbtcrpt;
r.v8.len = sizeof(r.v8.map);
r.v8.map = cpu_to_le32(val);
ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_REPORT_EN, &r.v8,
sizeof(r.v8));
struct rtw89_btc_btf_set_report_v8 v8;
struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
union { u64 v64; u32 v32; u16 v16; u8 v8; } u;
pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &u.v8);
"PBAR23SZ %hhu\n", u.v8);
pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &u.v8);
"PBAR45SZ %hhu\n", u.v8);
pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &u.v8);
"PBAR4SZ %hhu\n", u.v8);
pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &u.v8);
"PBAR5SZ %hhu\n", u.v8);
pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &u.v8);
"SBAR23SZ %hhu\n", u.v8);
pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &u.v8);
"SBAR45SZ %hhu\n", u.v8);
pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &u.v8);
"SBAR4SZ %hhu\n", u.v8);
pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &u.v8);
"SBAR5SZ %hhu\n", u.v8);
u8 v8;
v8 = rtw_read8(padapter, REG_CR+1);
v8 |= BIT(0); /* ENSWBCN */
rtw_write8(padapter, REG_CR+1, v8);
v8 = rtw_read8(padapter, REG_CR+1);
v8 &= ~BIT(0); /* ~ENSWBCN */
rtw_write8(padapter, REG_CR+1, v8);
u8 reg, v1, v2, v3, v4, v5, v6, v7, v8;
v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00;
v8 = bios[memtype + 56];
SiS_SetReg(SISSR, 0x1c, v8); /* ---- */
__u8 v8[8];
__u8 v8[8];
if (VERSION_LE(version, v8))
if (VERSION_GT(version, v8))
CHECK_VECTOR_REGISTER(v8);