arch/mips/cavium-octeon/octeon-platform.c
27
#define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
arch/mips/cavium-octeon/octeon-platform.c
28
#define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
arch/mips/include/asm/octeon/cvmx-address.h
292
#ifndef CVMX_ADD_IO_SEG
arch/mips/include/asm/octeon/cvmx-agl-defs.h
100
#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
101
#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
102
#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
103
#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
104
#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
31
#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
32
#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
33
#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
34
#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
35
#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
36
#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
37
#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
38
#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
39
#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
40
#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
41
#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
42
#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
43
#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
44
#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
45
#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
46
#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
47
#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
48
#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
49
#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
50
#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
51
#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
52
#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
53
#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
54
#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
55
#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
56
#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
57
#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
58
#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
59
#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
60
#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
61
#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
62
#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
63
#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
64
#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
65
#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
66
#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
67
#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
68
#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
69
#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
70
#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
71
#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
72
#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
73
#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
74
#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
75
#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
76
#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
77
#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
78
#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
79
#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
80
#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
81
#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
82
#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
83
#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
84
#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
85
#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
86
#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
87
#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
88
#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
89
#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
90
#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
91
#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
92
#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
93
#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-agl-defs.h
94
#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
95
#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
96
#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
97
#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
98
#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
arch/mips/include/asm/octeon/cvmx-agl-defs.h
99
#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
31
#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
32
#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
33
#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
34
#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
35
#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
36
#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
37
#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
38
#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
39
#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
40
#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
41
#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
42
#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
43
#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
44
#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
45
#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
46
#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
47
#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
48
#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
49
#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
50
#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
51
#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
52
#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
53
#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
54
#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
55
#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
arch/mips/include/asm/octeon/cvmx-asxx-defs.h
56
#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-ciu-defs.h
13
(CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
31
#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
32
#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
33
#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
34
#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
35
#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
36
#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
37
#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
38
#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
39
#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
40
#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
41
#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
42
#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
43
#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
44
#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
45
#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
46
#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
19
#define CVMX_CIU3_FUSE CVMX_ADD_IO_SEG(0x00010100000001A0ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
20
#define CVMX_CIU3_BIST CVMX_ADD_IO_SEG(0x00010100000001C0ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
21
#define CVMX_CIU3_CONST CVMX_ADD_IO_SEG(0x0001010000000220ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
22
#define CVMX_CIU3_CTL CVMX_ADD_IO_SEG(0x00010100000000E0ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
23
#define CVMX_CIU3_DESTX_IO_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000210000ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
24
#define CVMX_CIU3_DESTX_PP_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000200000ull) + ((offset) & 255) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
25
#define CVMX_CIU3_GSTOP CVMX_ADD_IO_SEG(0x0001010000000140ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
26
#define CVMX_CIU3_IDTX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010000110000ull) + ((offset) & 255) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
27
#define CVMX_CIU3_IDTX_IO(offset) (CVMX_ADD_IO_SEG(0x0001010000130000ull) + ((offset) & 255) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
28
#define CVMX_CIU3_IDTX_PPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001010000120000ull) + ((block_id) & 255) * 0x20ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
29
#define CVMX_CIU3_INTR_RAM_ECC_CTL CVMX_ADD_IO_SEG(0x0001010000000260ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
30
#define CVMX_CIU3_INTR_RAM_ECC_ST CVMX_ADD_IO_SEG(0x0001010000000280ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
31
#define CVMX_CIU3_INTR_READY CVMX_ADD_IO_SEG(0x00010100000002A0ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
32
#define CVMX_CIU3_INTR_SLOWDOWN CVMX_ADD_IO_SEG(0x0001010000000240ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
33
#define CVMX_CIU3_ISCX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010080000000ull) + ((offset) & 1048575) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
34
#define CVMX_CIU3_ISCX_W1C(offset) (CVMX_ADD_IO_SEG(0x0001010090000000ull) + ((offset) & 1048575) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
35
#define CVMX_CIU3_ISCX_W1S(offset) (CVMX_ADD_IO_SEG(0x00010100A0000000ull) + ((offset) & 1048575) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
36
#define CVMX_CIU3_NMI CVMX_ADD_IO_SEG(0x0001010000000160ull)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
37
#define CVMX_CIU3_SISCX(offset) (CVMX_ADD_IO_SEG(0x0001010000220000ull) + ((offset) & 255) * 8)
arch/mips/include/asm/octeon/cvmx-ciu3-defs.h
38
#define CVMX_CIU3_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001010000010000ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-dbg-defs.h
31
#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
31
#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
32
#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
33
#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
34
#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
35
#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
36
#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
37
#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
38
#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
39
#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
40
#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
41
#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
42
#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
43
#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
44
#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
45
#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
46
#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
47
#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
48
#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
49
#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
50
#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
51
#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
52
#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
53
#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
54
#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
55
#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
56
#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
57
#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
62
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
68
return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
71
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
72
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
74
return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
76
return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
arch/mips/include/asm/octeon/cvmx-dpi-defs.h
79
#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-fau.h
131
return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
arch/mips/include/asm/octeon/cvmx-fau.h
155
return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
31
#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
32
#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
33
#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
34
#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
35
#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
43
#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
44
#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
45
#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
46
#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
47
#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
48
#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
49
#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
50
#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
51
#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
52
#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
61
#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
62
#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
63
#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
64
#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
65
#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
66
#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
67
#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
68
#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull))
arch/mips/include/asm/octeon/cvmx-fpa-defs.h
69
#define CVMX_FPA_CLK_COUNT (CVMX_ADD_IO_SEG(0x00012800000000F0ull))
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
101
return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
108
return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
110
return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
112
return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
119
return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
121
return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
123
return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
130
return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
132
return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
134
return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
141
return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
143
return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
145
return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
152
return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
154
return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
156
return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
159
#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
160
#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
166
return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
168
return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
170
return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
177
return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
179
return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
181
return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
188
return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
190
return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
192
return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
195
#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
201
return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
203
return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
210
return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
212
return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
219
return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
221
return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
223
return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
230
return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
232
return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
234
return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
237
#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
242
return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
244
return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
246
return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
253
return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
255
return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
257
return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
264
return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
266
return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
268
return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
275
return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
277
return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
279
return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
286
return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
288
return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
290
return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
297
return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
299
return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
306
return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
308
return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
315
return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
317
return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
324
return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
326
return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
329
#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
330
#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
331
#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
336
return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
338
return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
35
return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
37
return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
44
return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
46
return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
53
return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
55
return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
57
return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
64
return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
66
return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
68
return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
75
return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
77
return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
79
return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
86
return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
88
return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
90
return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
97
return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
99
return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
31
#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
32
#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
33
#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
34
#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
35
#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
36
#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
37
#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
38
#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
39
#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
40
#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
41
#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
42
#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
arch/mips/include/asm/octeon/cvmx-gpio-defs.h
43
#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
arch/mips/include/asm/octeon/cvmx-iob-defs.h
31
#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
32
#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
33
#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
34
#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
35
#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
36
#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
37
#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
38
#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
39
#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
40
#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
41
#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
42
#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
43
#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
44
#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
45
#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
46
#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
47
#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
48
#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
49
#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
50
#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
51
#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
52
#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
53
#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
54
#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
55
#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
56
#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
57
#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
58
#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
59
#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
60
#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
61
#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
62
#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
63
#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
arch/mips/include/asm/octeon/cvmx-iob-defs.h
64
#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
31
#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
32
#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
33
#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
34
#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
35
#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
36
#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
37
#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
38
#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
39
#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
40
#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
41
#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
42
#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
43
#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
44
#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
45
#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
46
#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
47
#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
48
#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
49
#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
50
#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
51
#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
52
#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
53
#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
54
#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
55
#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
56
#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
57
#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
58
#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
59
#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
60
#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
61
#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
62
#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
63
#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
64
#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
65
#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
66
#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
67
#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
68
#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
69
#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
78
#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
79
#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
80
#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
81
#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
82
#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
83
#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
92
#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
93
#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
94
#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
95
#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
96
#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
97
#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
arch/mips/include/asm/octeon/cvmx-ipd-defs.h
98
#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
33
#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
34
#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
35
#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
37
(CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
39
(CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
40
#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
41
#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
42
#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
43
#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
49
#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
50
#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
51
#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
52
#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
53
#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
55
(CVMX_ADD_IO_SEG(0x0001180080A00400ull) + (((offset) & 3) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
57
#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
59
#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
61
#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
63
#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
65
#define CVMX_L2C_TADX_PRF(offset) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
67
#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
69
#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + \
arch/mips/include/asm/octeon/cvmx-l2c-defs.h
71
#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + \
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
31
#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
arch/mips/include/asm/octeon/cvmx-l2d-defs.h
32
#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
arch/mips/include/asm/octeon/cvmx-l2t-defs.h
33
#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
31
#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
32
#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
33
#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
34
#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
35
#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
36
#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
37
#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
38
#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
arch/mips/include/asm/octeon/cvmx-led-defs.h
39
#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-led-defs.h
40
#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-led-defs.h
41
#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-led-defs.h
42
#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
arch/mips/include/asm/octeon/cvmx-led-defs.h
43
#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
111
return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
113
return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
115
return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
117
return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
120
#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
121
#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
122
#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
123
#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
124
#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
125
#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
126
#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
127
#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
128
#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
138
return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
140
return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
142
return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
144
return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
147
#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
148
#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
149
#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
150
#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
151
#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull))
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
152
#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
153
#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
154
#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
155
#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
156
#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
157
#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
158
#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
159
#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
160
#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
161
#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
162
#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
163
#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
164
#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull))
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
165
#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull))
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
166
#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull))
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
167
#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
168
#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
169
#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
170
#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
171
#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
172
#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
173
#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
174
#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
175
#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
176
#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
177
#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
178
#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
179
#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
31
#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
32
#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
33
#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
34
#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
35
#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
36
#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
37
#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
38
#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
39
#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
40
#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
41
#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
42
#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
43
#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
44
#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
45
#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
46
#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
47
#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
48
#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
49
#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
50
#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
51
#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
52
#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
53
#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
54
#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
55
#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
56
#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
67
return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
69
return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
71
return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
73
return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
89
return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
91
return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
93
return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
95
return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
arch/mips/include/asm/octeon/cvmx-mio-defs.h
100
#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
101
#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
102
#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
103
#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
104
#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
105
#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
106
#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
107
#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
108
#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
109
#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
110
#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
111
#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
112
#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
113
#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
114
#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
115
#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
116
#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
117
#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
118
#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
119
#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
120
#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
121
#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
122
#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
123
#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
124
#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
125
#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
126
#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
127
#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
128
#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
129
#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
130
#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
131
#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
132
#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
133
#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
134
#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
135
#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
136
#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
137
#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
138
#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
139
#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
140
#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
141
#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
142
#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
143
#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
144
#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
145
#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
146
#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
147
#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
148
#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
149
#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
150
#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
151
#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
152
#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
153
#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
154
#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
155
#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
156
#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
157
#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
158
#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
159
#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
160
#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
161
#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
162
#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
163
#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
164
#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
165
#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
31
#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
32
#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
33
#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
34
#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
35
#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
36
#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
37
#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
38
#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
39
#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
40
#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
41
#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
42
#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
43
#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
44
#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
45
#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
46
#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
47
#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
48
#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
49
#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
50
#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
51
#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
52
#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
53
#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
54
#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
55
#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
56
#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
57
#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
58
#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
59
#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
60
#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
61
#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
62
#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-mio-defs.h
63
#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
64
#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
65
#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
66
#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
67
#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
68
#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
69
#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
70
#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
71
#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
72
#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
73
#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
74
#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
75
#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
76
#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
77
#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
78
#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
79
#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
80
#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
81
#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
82
#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
83
#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
84
#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
85
#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
86
#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
87
#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
88
#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
89
#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
90
#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
91
#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
92
#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
93
#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
94
#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
95
#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
96
#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
97
#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
98
#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
arch/mips/include/asm/octeon/cvmx-mio-defs.h
99
#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
31
#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
32
#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
33
#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
34
#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
35
#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
36
#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
37
#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
38
#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
39
#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
40
#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
41
#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
42
#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
43
#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
44
#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-mixx-defs.h
45
#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
100
#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
101
#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
102
#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
103
#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
104
#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
105
#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
106
#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
107
#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
108
#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
109
#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
110
#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
111
#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
112
#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
113
#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
114
#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
115
#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
116
#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
117
#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
118
#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
119
#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
120
#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
121
#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
122
#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
123
#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
124
#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
125
#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
126
#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
127
#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
128
#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
129
#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
130
#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
131
#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
132
#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
133
#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
134
#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
135
#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
136
#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
137
#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
138
#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
139
#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
140
#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
141
#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
142
#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
143
#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
144
#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
149
#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
150
#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
35
#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
40
#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
41
#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
46
#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
47
#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
48
#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
49
#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
50
#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
51
#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
52
#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
53
#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
54
#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
55
#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
56
#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
57
#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
58
#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
59
#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
60
#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
61
#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
66
#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
68
#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
73
#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
74
#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
91
#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
arch/mips/include/asm/octeon/cvmx-npi-defs.h
92
#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
93
#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
94
#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
95
#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
96
#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
97
#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
98
#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
arch/mips/include/asm/octeon/cvmx-npi-defs.h
99
#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
arch/mips/include/asm/octeon/cvmx-pci-defs.h
108
#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
100
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
107
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
110
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
114
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
116
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
118
return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
125
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
128
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
132
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
134
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
136
return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
143
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
146
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
150
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
152
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
154
return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
161
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
164
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
168
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
170
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
172
return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
179
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
182
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
186
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
188
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
190
return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
197
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
200
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
204
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
206
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
208
return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
215
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
218
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
222
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
224
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
226
return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
233
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
236
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
240
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
242
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
244
return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
251
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
254
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
258
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
260
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
262
return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
269
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
272
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
276
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
278
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
280
return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
287
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
290
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
294
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
296
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
298
return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
305
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
308
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
312
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
314
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
316
return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
323
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
326
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
330
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
332
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
334
return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
35
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
38
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
42
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
44
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
46
return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
53
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
56
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
60
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
62
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
64
return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
71
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
74
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
78
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
80
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
82
return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
89
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
92
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
96
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
98
return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
101
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
104
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
106
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
108
return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
117
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
120
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
122
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
124
return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
133
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
136
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
138
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
140
return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
149
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
152
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
154
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
156
return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
165
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
168
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
170
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
172
return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
181
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
184
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
186
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
188
return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
197
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
200
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
202
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
204
return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
213
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
216
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
218
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
220
return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
229
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
232
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
234
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
236
return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
245
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
248
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
250
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
252
return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
261
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
264
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
266
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
268
return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
37
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
40
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
42
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
44
return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
53
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
56
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
58
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
60
return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
69
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
72
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
74
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
76
return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
85
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
88
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
90
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
92
return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
31
#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
32
#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
33
#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
34
#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
35
#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
36
#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
37
#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
38
#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
39
#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
40
#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
41
#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
42
#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
43
#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
44
#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
45
#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
46
#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
47
#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
48
#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
49
#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
50
#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
51
#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
arch/mips/include/asm/octeon/cvmx-pemx-defs.h
52
#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
31
#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
32
#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
33
#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
34
#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
35
#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
36
#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
37
#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
38
#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
39
#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
40
#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
41
#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
42
#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
43
#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
44
#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
45
#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
arch/mips/include/asm/octeon/cvmx-pescx-defs.h
46
#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
100
#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
101
#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
102
#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
103
#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
104
#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
105
#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
106
#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
107
#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
108
#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
109
#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
110
#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
111
#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
112
#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
113
#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
114
#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
115
#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
116
#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
117
#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
118
#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
119
#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
120
#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
121
#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
122
#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
123
#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
124
#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
125
#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
126
#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
127
#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
128
#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
129
#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
130
#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
131
#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
132
#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
133
#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
134
#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
135
#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
136
#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
137
#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
138
#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
139
#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
140
#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
141
#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
142
#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
143
#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
144
#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
145
#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
146
#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
147
#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
148
#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
149
#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
150
#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
151
#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
152
#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
153
#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
154
#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
155
#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
156
#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
157
#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
158
#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
159
#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
160
#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
161
#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
162
#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
163
#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
164
#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
165
#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
166
#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
167
#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
168
#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
169
#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
170
#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
171
#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
172
#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
173
#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
174
#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
175
#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
176
#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
177
#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
178
#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
179
#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
180
#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
181
#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
182
#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
183
#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
184
#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
185
#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
186
#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
187
#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
188
#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
189
#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
190
#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
191
#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
192
#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
193
#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
194
#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
195
#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
196
#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
197
#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
198
#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
199
#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
200
#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
201
#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
202
#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
203
#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
204
#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
205
#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
206
#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
207
#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
208
#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
209
#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
210
#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
211
#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
212
#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
213
#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
214
#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
215
#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
216
#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
217
#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
218
#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
219
#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
220
#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
221
#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
222
#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
31
#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
32
#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
33
#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
34
#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
35
#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
36
#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
37
#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
38
#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
39
#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
40
#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
41
#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
42
#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
43
#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
44
#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
45
#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
46
#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
47
#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
48
#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
49
#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
50
#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
51
#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
52
#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
53
#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
54
#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
55
#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
56
#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
57
#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
58
#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
59
#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
60
#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
61
#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
62
#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
63
#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
64
#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
65
#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
66
#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
67
#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
68
#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
69
#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
70
#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
71
#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
72
#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
73
#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
74
#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
75
#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
76
#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
77
#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
78
#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
79
#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
80
#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
81
#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
82
#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
83
#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
84
#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
85
#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
86
#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
87
#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
88
#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
89
#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
90
#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
91
#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
92
#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
93
#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
94
#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
95
#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
96
#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
97
#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
98
#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pexp-defs.h
99
#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
100
#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
101
#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
102
#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
103
#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
104
#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
105
#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
106
#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
107
#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
108
#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
109
#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
110
#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
111
#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
112
#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
113
#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
114
#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
115
#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
116
#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
117
#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
118
#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
119
#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
120
#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
121
#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
122
#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
123
#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
124
#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
125
#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
126
#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
127
#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
128
#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
129
#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
130
#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
54
#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
55
#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
56
#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
57
#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
58
#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
59
#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
60
#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
61
#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
62
#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
63
#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
64
#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
65
#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
66
#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
67
#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
68
#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
69
#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
70
#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
71
#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
72
#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
73
#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
74
#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
75
#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
76
#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
77
#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
78
#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
79
#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
80
#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
81
#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull))
arch/mips/include/asm/octeon/cvmx-pip-defs.h
82
#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
83
#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
84
#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
85
#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
86
#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
87
#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
88
#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
89
#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
90
#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
91
#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
92
#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
93
#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
94
#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
95
#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
96
#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
97
#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
98
#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
arch/mips/include/asm/octeon/cvmx-pip-defs.h
99
#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
arch/mips/include/asm/octeon/cvmx-pko-defs.h
31
#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
32
#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
33
#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
34
#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
35
#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
36
#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
37
#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
38
#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
39
#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
40
#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
41
#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
42
#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
43
#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
44
#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
45
#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
46
#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
47
#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
48
#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
49
#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
50
#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
51
#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
52
#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
53
#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
54
#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
55
#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
56
#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
57
#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
58
#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
59
#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
60
#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
61
#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
62
#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-pko-defs.h
63
#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
64
#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-pko-defs.h
65
#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
66
#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
67
#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
68
#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
69
#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
70
#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
71
#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
72
#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8)
arch/mips/include/asm/octeon/cvmx-pko-defs.h
73
#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
74
#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
75
#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
76
#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
77
#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
78
#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
79
#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
80
#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
81
#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
82
#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
83
#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
84
#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
85
#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
86
#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull))
arch/mips/include/asm/octeon/cvmx-pko-defs.h
87
#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
31
#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
32
#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
33
#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
34
#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
35
#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
36
#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
37
#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
38
#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
39
#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
40
#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
41
#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
42
#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
43
#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
44
#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
45
#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
46
#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
47
#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
48
#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
49
#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
50
#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
51
#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
52
#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
53
#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
55
#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
56
#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
57
#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
arch/mips/include/asm/octeon/cvmx-pow-defs.h
58
#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
arch/mips/include/asm/octeon/cvmx-pow-defs.h
59
#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
arch/mips/include/asm/octeon/cvmx-rnm-defs.h
31
#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
arch/mips/include/asm/octeon/cvmx-rnm-defs.h
32
#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
arch/mips/include/asm/octeon/cvmx-rnm-defs.h
33
#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
arch/mips/include/asm/octeon/cvmx-rnm-defs.h
34
#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
arch/mips/include/asm/octeon/cvmx-rnm-defs.h
35
#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
31
#define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
32
#define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
33
#define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
34
#define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-rst-defs.h
35
#define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
36
#define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
37
#define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
38
#define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
39
#define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
40
#define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
arch/mips/include/asm/octeon/cvmx-rst-defs.h
41
#define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
arch/mips/include/asm/octeon/cvmx-rst-defs.h
42
#define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
31
#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
32
#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
33
#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
34
#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
35
#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
36
#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
37
#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
38
#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
39
#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
40
#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
41
#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
42
#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
43
#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
44
#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
45
#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-spxx-defs.h
46
#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
31
#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
32
#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
33
#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
34
#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
35
#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
36
#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
37
#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
38
#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
39
#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
40
#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
41
#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
42
#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
43
#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
44
#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
45
#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
46
#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
47
#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
48
#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
49
#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
50
#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
51
#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
52
#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
53
#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
54
#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
55
#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
56
#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
57
#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
58
#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
59
#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
60
#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
61
#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
62
#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
63
#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
64
#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
65
#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
66
#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
67
#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
68
#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
69
#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
70
#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
71
#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
72
#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
73
#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
74
#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
75
#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
76
#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-sriox-defs.h
77
#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
31
#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
32
#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
33
#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
34
#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
35
#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-srxx-defs.h
36
#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
31
#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
32
#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
33
#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
34
#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
35
#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
36
#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
37
#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
38
#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
39
#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
40
#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
41
#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
42
#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
43
#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
44
#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
45
#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-stxx-defs.h
46
#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
31
#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
32
#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
33
#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
34
#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
35
#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
36
#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
37
#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
38
#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
39
#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
40
#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
41
#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
42
#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
43
#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
arch/mips/include/asm/octeon/cvmx.h
52
#ifndef CVMX_ADD_IO_SEG
arch/mips/pci/pcie-octeon.c
1893
set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
arch/mips/pci/pcie-octeon.c
1941
CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
arch/mips/pci/pcie-octeon.c
2022
CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
drivers/mmc/host/cavium-octeon.c
22
#define CVMX_MIO_BOOT_CTL CVMX_ADD_IO_SEG(0x00011800000000D0ull)
drivers/spi/spi-cavium.h
36
#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
drivers/spi/spi-cavium.h
37
#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
drivers/spi/spi-cavium.h
38
#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
drivers/spi/spi-cavium.h
39
#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
drivers/usb/host/octeon-hcd.h
55
(CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \
drivers/usb/host/octeon-hcd.h
58
(CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \
drivers/usb/host/octeon-hcd.h
90
(CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid))
drivers/usb/host/octeon-hcd.h
92
(CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid))
drivers/watchdog/octeon-wdt-main.c
90
#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
