Symbol: CV1800_CLK_BIT
drivers/clk/sophgo/clk-cv1800.c
111
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 2),
drivers/clk/sophgo/clk-cv1800.c
112
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
drivers/clk/sophgo/clk-cv1800.c
125
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 3),
drivers/clk/sophgo/clk-cv1800.c
126
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
drivers/clk/sophgo/clk-cv1800.c
139
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 4),
drivers/clk/sophgo/clk-cv1800.c
140
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
drivers/clk/sophgo/clk-cv1800.c
153
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 5),
drivers/clk/sophgo/clk-cv1800.c
154
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
drivers/clk/sophgo/clk-cv1800.c
83
.en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 2),
drivers/clk/sophgo/clk-cv1800.c
84
.clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
drivers/clk/sophgo/clk-cv1800.c
97
.en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 3),
drivers/clk/sophgo/clk-cv1800.c
98
.clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
drivers/clk/sophgo/clk-cv18xx-ip.h
123
.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
drivers/clk/sophgo/clk-cv18xx-ip.h
143
.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
drivers/clk/sophgo/clk-cv18xx-ip.h
154
.gate = CV1800_CLK_BIT(_gate_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
186
.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
drivers/clk/sophgo/clk-cv18xx-ip.h
203
.gate = CV1800_CLK_BIT(_gate_reg, _gate_shift),\
drivers/clk/sophgo/clk-cv18xx-ip.h
218
.bypass = CV1800_CLK_BIT(_bypass_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
220
.clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
238
.src_en = CV1800_CLK_BIT(_src_en_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
240
.output_en = CV1800_CLK_BIT(_output_en_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
242
.div_en = CV1800_CLK_BIT(_div_en_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
244
.div_up = CV1800_CLK_BIT(_div_up_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
74
.gate = CV1800_CLK_BIT(_gate_reg, _gate_shift), \
drivers/clk/sophgo/clk-cv18xx-ip.h
83
.gate = CV1800_CLK_BIT(_gate_reg, \
drivers/clk/sophgo/clk-cv18xx-ip.h
98
.gate = CV1800_CLK_BIT(_gate_reg, \
drivers/clk/sophgo/clk-cv18xx-pll.h
107
.pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
drivers/clk/sophgo/clk-cv18xx-pll.h
109
.pll_status = CV1800_CLK_BIT(_pll_status_reg, \
drivers/clk/sophgo/clk-cv18xx-pll.h
90
.pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
drivers/clk/sophgo/clk-cv18xx-pll.h
92
.pll_status = CV1800_CLK_BIT(_pll_status_reg, \