v31
sm4e b0.4s, v31.4s; \
sm4e b1.4s, v31.4s; \
sm4e b2.4s, v31.4s; \
sm4e b3.4s, v31.4s; \
sm4e b4.4s, v31.4s; \
sm4e b5.4s, v31.4s; \
sm4e b6.4s, v31.4s; \
sm4e b7.4s, v31.4s; \
sm4e b0.4s, v31.4s; \
sm4e b0.4s, v31.4s; \
sm4e b1.4s, v31.4s; \
sm4e b0.4s, v31.4s; \
sm4e b1.4s, v31.4s; \
sm4e b2.4s, v31.4s; \
sm4e b3.4s, v31.4s; \
ld1 {v28.16b-v31.16b}, [ptr];
.ifc \vxr,%v31
le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
struct atom_umc_info_v3_1 v31;
struct atom_firmware_info_v3_1 v31;
umc_config = le32_to_cpu(umc_info->v31.umc_config);
fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
struct atom_smu_info_v3_1 v31;
le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
uint32_t v0, v1, v28, v31;
v31 = REG_GET_FIELD(hw_assert_mskhi,
if (v0 && v1 && v28 && v31)
else if (!v0 && !v1 && !v28 && !v31)
v0, v1, v28, v31);
uint32_t v0, v1, v28, v31;
v31 = REG_GET_FIELD(hw_assert_mskhi,
if (v0 && v1 && v28 && v31)
else if (!v0 && !v1 && !v28 && !v31)
v0, v1, v28, v31);
stvx v31,reg,%r1;
lvx v31,reg,%r1;
lvx v31,r5,r3
CHECK_VECTOR_REGISTER(v31);
void *data, *v31;
v31 = (void *)(data + size + v_regset_hdr->vlenb * 31);
ksft_test_result(*(int *)v31 == child_set_val, "GETREGSET vector\n");
*(int *)v31 = parent_set_val;