arch/s390/include/asm/fpu-insn-asm.h

154

.ifc \vxr,%v20

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

132

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

155

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[pipe->pipe_idx],

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

62

bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

704

bool is_plane_duplicate = ctx->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

710

ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index) &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

145

} v20;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c

903

vstartup = dml_get_vstartup_calculated(&ctx->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1140

if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream->stream_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1153

bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1186

if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1200

struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1277

dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1287

dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] =

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1301

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1302

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1303

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1304

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1308

dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1309

dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1310

dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1311

dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1312

if (dml2->v20.dml_core_ctx.ip.hostvm_enable)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1313

dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1344

dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1347

dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_4to1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1353

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1354

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1361

context->streams[i], &dml2->v20.dml_core_ctx.soc);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1365

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1376

populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1380

&dml2->v20.dml_core_ctx.soc);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1388

dml2->v20.dml_core_ctx.policy.ImmediateFlipRequirement[disp_cfg_plane_location] = dml_immediate_flip_not_required;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1397

&dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1398

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1405

dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1408

dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_4to1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1419

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1420

dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

279

switch (dml2->v20.dml_core_ctx.project) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

331

struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

332

struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

335

unsigned int dml_project = dml2->v20.dml_core_ctx.project;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

350

p->in_states = &dml2->v20.scratch.create_scratch.in_states;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

354

switch (dml2->v20.dml_core_ctx.project) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

36

switch (dml2->v20.dml_core_ctx.project) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

506

if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

507

(dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

513

} else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

514

dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

515

dml2->v20.dml_core_ctx.project != dml_project_dcn351) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

562

if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

563

dml2->v20.dml_core_ctx.project == dml_project_dcn36 ||

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

564

dml2->v20.dml_core_ctx.project == dml_project_dcn351) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

796

if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

797

out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

198

if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

209

if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

220

bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

283

struct dml2_calculate_rq_and_dlg_params_scratch *s = &in_ctx->v20.scratch.calculate_rq_and_dlg_params_scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

285

context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

288

if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

296

context->bw_ctx.bw.dcn.compbuf_size_kb = in_ctx->v20.dml_core_ctx.ip.config_return_buffer_size_in_kbytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

307

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

315

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[dml_pipe_idx]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

316

ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

321

populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

329

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

331

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

335

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

339

dml_rq_dlg_get_rq_reg(&s->rq_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

340

dml_rq_dlg_get_dlg_reg(&s->disp_dlg_regs, &s->disp_ttu_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

343

context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

364

context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

366

context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

524

in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

531

total_det_allocated += dml_get_det_buffer_size_kbytes(&in_ctx->v20.dml_core_ctx, dml_pipe_idx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c

539

det_scratch->dpps_per_surface[i] = in_ctx->v20.scratch.cur_display_config.hw.DPPPerSurface[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

51

(*dml2)->v20.dml_core_ctx.project = dml_project_dcn35;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

54

(*dml2)->v20.dml_core_ctx.project = dml_project_dcn351;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

57

(*dml2)->v20.dml_core_ctx.project = dml_project_dcn36;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

60

(*dml2)->v20.dml_core_ctx.project = dml_project_dcn32;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

63

(*dml2)->v20.dml_core_ctx.project = dml_project_dcn321;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

66

(*dml2)->v20.dml_core_ctx.project = dml_project_dcn401;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

69

(*dml2)->v20.dml_core_ctx.project = dml_project_default;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

75

initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

77

initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c

79

initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

100

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

102

s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

105

s->mode_support_params.in_start_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

161

struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

162

struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

167

build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

192

for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

193

s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

197

for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

198

dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

206

dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_global->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

210

dml2_extract_watermark_set(&dml2->v20.g6_temp_read_watermark_set, &dml2->v20.dml_core_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

211

dml2->v20.g6_temp_read_watermark_set.cstate_pstate.fclk_pstate_change_ns = dml2->v20.g6_temp_read_watermark_set.cstate_pstate.pstate_change_ns;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

215

while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram_speed_mts)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

222

for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

223

dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latencies[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

270

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

274

build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

312

s->cur_policy = dml2->v20.dml_core_ctx.policy;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

313

s->optimize_configuration_params.dml_core_ctx = &dml2->v20.dml_core_ctx;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

315

s->optimize_configuration_params.ip_params = &dml2->v20.dml_core_ctx.ip;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

323

dml2->v20.dml_core_ctx.policy = s->new_policy;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

338

dml2->v20.dml_core_ctx.policy = s->cur_policy;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

368

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

391

result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

393

result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

403

struct dml2_wrapper_scratch *s = &dml2->v20.scratch;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

414

out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

415

out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

416

out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

417

out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

418

out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

419

out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

426

memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

427

memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

428

memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

429

memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

464

out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

467

(lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

468

lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

469

out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

472

out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

473

out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

474

out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

475

out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

476

out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

477

out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

486

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

487

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

489

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.dml_core_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

491

memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

492

dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

493

dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

495

context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

520

memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

521

memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

522

memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

523

memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

525

build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

527

map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

529

dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

532

&dml2->v20.scratch.cur_display_config,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

533

&dml2->v20.scratch.mode_support_info,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

537

result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

567

*fclk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

568

*dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

74

if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

75

dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

76

dml2->v20.dml_core_ctx.project != dml_project_dcn351) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

86

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

87

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

88

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

89

dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true;

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

357

v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20)\

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

378

FN(reg, f20), v20)

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c

138

u8 v20 = (1 << (j + 1)) % gr->tpc_total;

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c

143

(v20 << 8) |

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

567

u32 rcpi, ib_rssi, wb_rssi, v20, v21;

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

593

v20 = le32_to_cpu(rxv[20]);

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

596

foe = FIELD_GET(MT_CRXV_FOE_LO, v20) |

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

599

snr = FIELD_GET(MT_CRXV_SNR, v20) - 16;

tools/testing/selftests/powerpc/include/vmx_asm.h

11

stvx v20,reg,%r1; \

tools/testing/selftests/powerpc/include/vmx_asm.h

38

lvx v20,reg,%r1; \

tools/testing/selftests/powerpc/include/vmx_asm.h

68

lvx v20,r5,r3

tools/testing/selftests/riscv/vector/v_exec_initval_nolibc.c

74

CHECK_VECTOR_REGISTER(v20);