v18
.ifc \vxr,%v18
v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19)\
FN(reg, f18), v18, \
v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20)\
FN(reg, f18), v18, \
u32 mask, off, v13, v18;
.v18 = DM1105_LNB_18V,
.v18 = DM1105_LNB_18V,
.v18 = DM1105_LNB_18V,
.v18 = DM05_LNB_18V,
.v18 = UNBR_LNB_18V,
dm1105_boards[dev->boardnr].lnb.v18);
u32 v18 = SDMMC_UHS_18V << slot->id;
uhs &= ~v18;
uhs |= v18;
ret, uhs & v18 ? "1.8" : "3.3");
CHECK_VECTOR_REGISTER(v18);